Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a fir
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.
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1. An integrated circuit (IC) comprising: at least one reconfigurable circuit for configurably performing a plurality of operations, each operation selected by a reconfiguration signal; anda reconfiguration signal generator for generating a value of the reconfiguration signal,wherein said reconfigur
1. An integrated circuit (IC) comprising: at least one reconfigurable circuit for configurably performing a plurality of operations, each operation selected by a reconfiguration signal; anda reconfiguration signal generator for generating a value of the reconfiguration signal,wherein said reconfiguration signal generator generates N unique values of the reconfiguration signal during a particular time interval and M unique values during a different time interval, wherein a duration of the particular time interval is equal to a duration of the different time interval, wherein N and M are positive integers and N is less than M,wherein said reconfiguration signal generator generates fewer unique values of the reconfiguration signal during the particular time interval than during the different time interval by using a particular value during at least two reconfiguration intervals within the particular time interval while using the particular value during only one reconfiguration interval within the different time interval. 2. The IC of claim 1, wherein the reconfiguration signal generator generates the value of the reconfiguration signal based on at least one programming signal. 3. The IC of claim 1, wherein the reconfiguration signal comprises a plurality of bits for encoding the reconfiguration signal using a Gray code encoding scheme. 4. The IC of claim 1, wherein the reconfiguration signal comprises a plurality of bits for encoding the reconfiguration signal using a one-hot encoding scheme. 5. The IC of claim 1, wherein the duration of the particular time interval and the duration of the different time interval are equal to a duration of a period of a primary cycle of the IC. 6. The IC of claim 1, wherein the reconfiguration signal is for selecting a configuration data set from among a plurality of configuration data sets, wherein each configuration data set specifies an operation from among the plurality of operations. 7. The IC of claim 6 further comprising a storage for storing the plurality of configuration data sets. 8. The IC of claim 6 further comprising a via programmable array for providing the configuration data sets, wherein the reconfiguration signal selects a configuration data set from among the plurality of configuration data sets provided by the via programmable array. 9. A method of implementing an integrated circuit (IC) design in an IC comprising at least one reconfigurable circuit for configurably performing a plurality of operations, the method comprising: generating a reconfiguration signal for selecting an operation from among the plurality of operations; andeach time a value of the reconfiguration signal changes, reconfiguring the reconfigurable circuit to perform the operation selected by the reconfiguration signal,wherein said generated reconfiguration signal assumes N unique values during a particular time interval and assumes M unique values during a different time interval, wherein the particular time interval and the different time interval have a same duration, wherein N and M are positive integers and N is less than M. 10. The method of claim 9, wherein the reconfiguration signal assumes fewer unique values during the particular time interval than during the different time interval by assuming a particular value during at least two reconfiguration intervals within the particular time interval while assuming the particular value during only one reconfiguration interval within the different time interval. 11. The method of claim 9, wherein said generating is based on at least one programming signal. 12. The method of claim 9, wherein the reconfiguration signal comprises a plurality of bits for encoding the reconfiguration signal using a Gray code encoding scheme. 13. The method of claim 9, wherein the reconfiguration signal comprises a plurality of bits for encoding the reconfiguration signal using a one-hot encoding scheme. 14. The method of claim 9, wherein the duration of the particular time interval and the duration of the different time interval are equal to a duration of a period of a primary cycle of the IC design. 15. The method of claim 9, wherein the reconfiguration signal is for selecting a configuration data set from among a plurality of configuration data sets, wherein each configuration data set specifies an operation from among the plurality of operations. 16. The method of claim 15, wherein the IC further comprises a storage for storing the configuration data sets. 17. The method of claim 15, wherein the IC further comprises a via programmable array for providing the configuration data sets, wherein the reconfiguration signal selects a configuration data set from among the plurality of configuration data sets provided by the via programmable array. 18. An electronic device comprising: a memory device for providing configuration data; andan integrated circuit (“IC”) comprising: at least one reconfigurable circuit for configurably performing a plurality of operations based on the provided configuration data, each operation selected by a reconfiguration signal; anda reconfiguration signal generator for generating a value of the reconfiguration signal,wherein said reconfiguration signal generator generates N unique values of the reconfiguration signal during a particular time interval and M unique values during a different time interval, wherein a duration of the particular time interval is equal to a duration of the different time interval, wherein N and M are positive integers and N is less than M. 19. The electronic device of claim 18, wherein the reconfiguration signal assumes fewer unique values during the particular time interval than during the different time interval by assuming a particular value during at least two reconfiguration intervals within the particular time interval while assuming the particular value during only one reconfiguration interval within the different time interval. 20. The electronic device of claim 18, wherein the reconfiguration signal generator generates the value of the reconfiguration signal based on at least one programming signal. 21. The electronic device of claim 18, wherein the reconfiguration signal comprises a plurality of bits for encoding the reconfiguration signal using a Gray code encoding scheme. 22. The electronic device of claim 18, wherein the reconfiguration signal comprises a plurality of bits for encoding the reconfiguration signal using a one-hot encoding scheme. 23. The electronic device of claim 18, wherein the duration of the particular time interval and the duration of the different time interval are equal to a duration of a period of a clock cycle of a circuit design. 24. The electronic device of claim 18, wherein the reconfiguration signal is for selecting a configuration data set from among a plurality of configuration data sets stored in the memory device, wherein each configuration data set specifies an operation from among the plurality of operations. 25. The electronic device of claim 24 further comprising a via programmable array for providing the configuration data sets, wherein the reconfiguration signal selects a configuration data set from among the plurality of configuration data sets provided by the via programmable array. 26. An integrated circuit (IC) comprising: at least one reconfigurable circuit for configurably performing a plurality of operations; anda reconfiguration signal generator for generating a reconfiguration signal for selecting an operation from among the plurality of operations, said reconfiguration signal comprising K phases for each of a plurality of time intervals of equal duration,wherein each of the K phases assumes one of N unique values during a first time interval and one of M unique values during a second time interval, wherein N and M are positive integers and N is less than M. 27. The IC of claim 26, wherein K is less than N and each of the K phases of the first time interval assumes a different unique value. 28. The IC of claim 26, wherein K is greater than M, wherein at least two of the K phases in the first time interval assume a same unique value. 29. The IC of claim 26, wherein K is greater than N, wherein at least two of the K phases in the second time interval assume a same unique value.
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Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
Azegami Kengo,JPX ; Yamashita Koichi,JPX, Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Configuration modes for a time multiplexed programmable logic device.
Wakayama Shigetoshi,JPX ; Gotoh Kohtaroh,JPX ; Saito Miyoshi,JPX ; Ogawa Junji,JPX, Destructive read type memory circuit, restoring circuit for the same and sense amplifier.
Inoue Kazunari (Hyogo JPX) Fudeyasu Yoshio (Hyogo JPX), Dual port memory effecting transfer of data between a serial register and an arbitrary memory block.
Nguyen Bai ; Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Wong Jack T. ; Chang Herman M., Efficient interconnect network for use in FPGA device having variable grain architecture.
Kant,Shree; Tam,Kenway; Kongetira,Poonacha P.; Lin,Yuan Jung D; Liu,Zhen W.; Aingaran,Kathirgamar, Efficient method of data transfer between register files and memories.
Agrawal, Om P.; Fontana, Fabiano; Bosco, Gilles M., Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use.
Tavana Danesh (Mountain View CA) Yee Wilson K. (Tracy CA) Holen Victor A. (Saratoga CA), FPGA architecture with repeatable tiles including routing matrices and logic matrices.
Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA), Flexible high impedance control in a cole cell in a configurable logic array.
Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
Furumochi Kazuto,JPX ; Seino Junji,JPX, MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary.
Sharpe-Geisler Bradley A. (San Jose CA), Macrocell and clock signal allocation circuit for a programmable logic device (PLD) enabling PLD resources to provide mu.
Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
Poplingher Mircea ; Chen Wenliang ; Suryanarayanan Ganesh ; Chen Wayne W. ; Lo Roger Y., Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle.
Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
Motomura Masato,JPX, Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
Blodget, Brandon J.; McMillan, Scott P.; James-Roxby, Philip B.; Sundararajan, Prasanna; Keller, Eric R.; Curd, Derek R.; Kalra, Punit S.; LeBlanc, Richard J.; Eck, Vincent P., Reconfiguration of a programmable logic device using internal control.
Om P. Agrawal ; Claudia A. Stanley ; Xiaojie (Warren) He ; Larry R. Metzger ; Robert A. Simon ; Kerry A. Ilgenstein, Scalable architecture for high density CPLD's having two-level hierarchy of routing resources.
Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Tran Giap H., Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits.
Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
Balasubramanian,Rabindranath; Zhu,Limin; Speers,Theodore; Bakker,Gregory, System-on-a-chip integrated circuit including dual-function analog and digital inputs.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
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