최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0840477 (2010-07-21) |
등록번호 | US-8312200 (2012-11-13) |
우선권정보 | DE-199 26 538 (1999-06-10); DE-100 00 423 (2000-01-09); DE-100 18 119 (2000-04-12) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 562 |
Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.
1. A processor chip comprising: an arrangement of a plurality of processor cores;at least one memory controller for external main memory; anda plurality of cache elements for caching data, the plurality of cache elements being located between and connected to the processor cores and the at least one
1. A processor chip comprising: an arrangement of a plurality of processor cores;at least one memory controller for external main memory; anda plurality of cache elements for caching data, the plurality of cache elements being located between and connected to the processor cores and the at least one memory controller;wherein each of at least some of the plurality of processor cores: operates as at least one of an accumulator processor, a stack processor, and a load/store processor; andincludes a unit for loading instructions defining at least one of a function and an interconnection of the respective processor core. 2. The processor chip according to claim 1, wherein the at least one memory controller is adapted to control external Random Access Memory (RAM). 3. The processor chip according to claim 1, wherein at least some of the processor cores are reconfigurable in at least one of function and interconnection. 4. The processor chip according to claim 1, wherein the at least one memory controller supports cache functions. 5. The processor chip according to claim 1, wherein the at least one memory controller has an associated memory management unit (MMU). 6. The processor chip according to claim 1, further comprising: at least one of interface controller for peripheral devices. 7. The processor chip according to claim 1, wherein the each of the at least some of the plurality of processor cores is reconfigurable in at least one of its function and its interconnection as defined by the instructions and on a hardware level by changing its active circuitry paths. 8. The processor chip according to claim 7, wherein the at least one memory controller is adapted to control external Synchronous Dynamic Random Access Memory (SDRAM). 9. The processor chip according to claim 7, wherein the at least one memory controller is adapted to control external Rambus Dynamic Random Access Memory (RDRAM). 10. The processor chip according to claim 7, wherein the at least one memory controller has an associated cache TAG memory. 11. The processor chip according to claim 7, further comprising: an Ethernet controller adapted for operating as an interface controller for peripheral devices. 12. The processor chip according to claim 7, further comprising: a peripheral component interconnect (PCI) controller. 13. The processor chip according to claim 7, wherein the changing of the active circuitry paths is performed using a switching device. 14. The processor chip according to claim 7, wherein the at least one memory controller is adapted to control external Dynamic Random Access Memory (DRAM). 15. A processor chip comprising: an arrangement of a plurality of processor cores;at least one memory controller for Dynamic Random Access Memory (DRAM); anda plurality of cache elements for caching data, the plurality of cache elements being located between and connected to the processor cores and the at least one memory controller;wherein each of at least some of the processor cores: operates as at least one of an accumulator processor, a stack processor, and a load/store processor; andincludes a unit for loading instructions defining at least one of a function and an interconnection of the respective processor core. 16. The processor chip according to claim 15, wherein the at least one memory controller is adapted to control external memory. 17. The processor chip according to claim 15, wherein the at least one memory controller is adapted to control external Random Access Memory (RAM). 18. The processor chip according to claim 15, wherein at least some of the processor cores are reconfigurable in at least one of function and interconnection. 19. The processor chip according to claim 15, wherein the at least one memory controller supports cache functions. 20. The processor chip according to claim 15, wherein the at least one memory controller has an associated memory management unit (MMU). 21. The processor chip according to claim 15, further comprising: at least one interface controller for peripheral devices. 22. The processor chip according to claim 15, wherein the each of the at least some of the processor cores is reconfigurable in at least one of its function and its interconnection as defined by the instructions and on a hardware level by changing its active circuitry paths. 23. The processor chip according to claim 22, wherein the at least one memory controller is adapted to control external Rambus Dynamic Random Access Memory (RDRAM). 24. The processor chip according to claim 22, wherein the at least one memory controller has an associated cache TAG memory. 25. The processor chip according to claim 22, further comprising: an Ethernet controller adapted for operating as an interface controller for peripheral devices. 26. The processor chip according to claim 22, further comprising: a peripheral component interconnect (PCI) controller. 27. The processor chip according to claim 22, further comprising: at least one interface controller for peripheral devices., wherein the at least one memory controller is adapted to control external Rambus Dynamic Random Access Memory (RDRAM). 28. The processor chip according to claim 22, further comprising: at least one interface controller for peripheral devices, wherein the at least one memory controller has an associated cache TAG memory. 29. The processor chip according to claim 22, wherein the changing of the active circuitry paths is performed using a switching device. 30. The processor chip according to claim 22, wherein the at least one memory controller is adapted to control external Synchronous Dynamic Random Access Memory (SDRAM). 31. The processor chip according to claim 22, further comprising: at least one interface controller for peripheral devices, wherein the at least one memory controller is adapted to control external Synchronous Dynamic Random Access Memory (SDRAM). 32. The processor chip according to claim 21, wherein the at least one memory controller is adapted to control external memory. 33. The processor chip according to claim 21, wherein the at least one memory controller is adapted to control external Random Access Memory RAM. 34. The processor chip according to claim 21, wherein the at least one memory controller supports cache functions. 35. The processor chip according to claim 21, wherein the at least one memory controller has an associated memory management unit (MMU). 36. A processor chip comprising: an arrangement of a plurality of processor cores;at least one interface controller for peripheral devices; anda plurality of cache elements for caching data, the plurality of cache elements being located between and connected to the processor cores and the at least one memory controller;wherein each of at least some of the processor cores: is reconfigurable in at least one of its function and its interconnection, and on a hardware level by changing, via a switching device, its active circuitry paths;operates as at least one of an accumulator processor, a stack processor, and a load/store processor; andincludes a unit for loading instructions defining at least one of the function and the interconnection according to which the respective processor core is configured. 37. The processor chip according to claim 36, wherein at least some of the processor cores are reconfigurable in at least one of function and interconnection. 38. The processor chip according to claim 36, wherein the each of the at least some of the processor cores is reconfigurable in at least one of its function and its interconnection as defined by the instructions and on a hardware level by changing its active circuitry paths. 39. The processor chip according to claim 31, wherein the at least interface controller is an Ethernet controller. 40. The processor chip according to claim 31, wherein the at least one interface controller is a peripheral component interconnect (PCI) controller. 41. The processor chip according to claim 31, wherein the at least one interface controller is a universal serial bus (USB) controller. 42. The processor chip according to claim 38, wherein the changing of the active circuitry paths is performed using a switching device.
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