IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0098391
(2008-04-04)
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| 등록번호 |
US-8312362
(2012-11-13)
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발명자
/ 주소 |
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| 출원인 / 주소 |
- Marvell Israel (M.I.S.L) Ltd.
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| 인용정보 |
피인용 횟수 :
0 인용 특허 :
58 |
초록
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A data partitioning circuit partitions received data and an appended error checking code into a plurality of data lines having a fixed length and a last line. A vector selector inserts a pad vector after the appended error checking code when the last line is less than the first length and not equal
A data partitioning circuit partitions received data and an appended error checking code into a plurality of data lines having a fixed length and a last line. A vector selector inserts a pad vector after the appended error checking code when the last line is less than the first length and not equal to the first fixed length minus a length of the appended error checking code, and selects one of a plurality of error checking vectors, the pad vector having a length providing the last line with the first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector. An error checking code calculation circuit performs error checking calculations on the plurality of data lines and the last line to generate an error checking result.
대표청구항
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1. A method of determining or confirming an error in transmitted data, comprising: receiving transmitted data and then partitioning the received data into a plurality of data lines each having a first fixed length, and a last line containing an error checking code calculated on said transmitted data
1. A method of determining or confirming an error in transmitted data, comprising: receiving transmitted data and then partitioning the received data into a plurality of data lines each having a first fixed length, and a last line containing an error checking code calculated on said transmitted data;when said last line is less than said first length, appending to the last line a pad vector that is dimensioned to make the last line, including the appended pad vector, the first length;performing an error checking calculation on the plurality of data lines and on the last line including the error checking code and the pad vector to calculate an error checking result;determining a state of the calculated error checking result; andindicating an error or an absence of an error in the transmitted data based on the calculated error checking result. 2. The method of claim 1, wherein the plurality of data lines each comprise a plurality of data blocks, each data block having a second fixed length, said second fixed length being an integer divisor of said first fixed length, and said appended error checking code has a third length comprising an integer multiple of said second fixed length, said integer multiple being the same as or less than said integer divisor. 3. The method of claim 1, wherein said first fixed length comprises 2m bits, where m is an integer of from 6 to 10. 4. The method of claim 1, wherein performing said error checking calculation comprises error checking each of the plurality of data lines and the last line with common error checking circuitry. 5. The method of claim 1, wherein performing said error checking calculation on the plurality of data lines comprises a plurality of cyclic redundancy check (CRC) calculations. 6. The method of claim 5, wherein said appended error checking code comprises a CRC calculation result on said transmitted data. 7. The method of claim 1, wherein said appended error checking code has a length of p bits, where p is an integer of from 8 to 128. 8. The method of claim 7, wherein p is 8, 16, 32, 64 or 128. 9. The method of claim 1, wherein the state of the calculated error checking result is selected from the group consisting of all zeros and all ones. 10. The method of claim 9, wherein if the calculated error checking result does not have said predetermined state, indicating that there is an error in said transmitted data. 11. A circuit for determining a data transmission error and/or checking a data transmission error determination, comprising: a data partitioning circuit configured to receive transmitted data and an appended error checking code calculated on said transmitted data, and partition said received data and said appended error checking code into a plurality of data lines having a fixed length and a last line containing the appended error checking code;a vector selector configured to insert a pad vector after said appended error checking code when the last line is less than said first length and not equal to said first fixed length minus a length of said appended error checking code, and select one of a plurality of error checking vectors, the pad vector having a length providing said last line with said first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector; andan error checking code calculation circuit configured to perform error checking calculations on the plurality of data lines and the last line to generate an error checking result;a logic circuit configured to indicate an error or an absence of an error in the transmitted data based on the calculated error checking result. 12. The circuit of claim 11, wherein said pad vector comprises a zero-pad vector. 13. The circuit of claim 11, wherein said fixed length is 2m bits, where m is an integer of from 6 to 10. 14. The circuit of claim 11, wherein said transmitted data comprises a packet or frame. 15. The circuit of claim 11, wherein said error checking code calculation circuit comprises a cyclic redundancy checking (CRC) circuit. 16. The circuit of claim 11, wherein said logic circuit further comprises a demultiplexer configured to output transmitted data error checking code calculated on said transmitted data or said error checking result, depending on a control signal state. 17. The circuit of claim 11, wherein vector selector further selects the pad vector from a set of pad vectors, each having a unique length. 18. The circuit of claim 17, further comprising a storage circuit configured to store said set of pad vectors. 19. The circuit of claim 18, wherein said storage circuit comprises a hash table or a look-up table. 20. The circuit of claim 17, further comprising a remainder logic circuit configured to generate a remainder information signal having a state corresponding to a length of said remainder. 21. The circuit of claim 20, wherein said vector selector selects said one of said pad vectors in response to said remainder information signal. 22. A receiver, comprising: a data partitioning circuit configured to receive transmitted data and an appended error checking code calculated on said transmitted data, and partition said received data and said appended error checking code into a plurality of data lines having a fixed length and a last line containing the appended error checking code;a vector selector configured to insert a pad vector after said appended error checking code when the last line is less than said first length and not equal to said first fixed length minus a length of said appended error checking code, and select one of a plurality of error checking vectors, the pad vector having a length providing said last line with said first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector;an error checking code calculation circuit configured to perform error checking calculations on the plurality of data lines and the last line to generate an error checking result;a logic circuit configured to indicate an error or an absence of an error in the transmitted data based on the calculated error checking result;a processor in communication with said data partitioning circuit, configured to process said received data; anda clock recovery circuit configured to recover a clock signal from said received data. 23. The receiver of claim 22, embodied on a single integrated circuit. 24. The receiver of claim 22, wherein said data partitioning circuit comprises a deserializer configured to convert serial digital data into parallel digital data for processing by said error checking code calculation circuit. 25. The receiver of claim 22, wherein said transmitted data comprises a packet or frame. 26. The receiver of claim 25, wherein said processor is further configured to assemble (i) non-data information from said packet or frame and (ii) at least part of said received data. 27. The receiver of claim 26, further comprising a decoder configured to decode at least part of said non-data information. 28. A system for transferring data on or across a network, comprising: the receiver of claim 22;at least one transmitter in communication with said receiver, said transmitter being configured to transmit said transmitted data to said receiver; andat least one receiver port in communication with said receiver for receiving said transmitted data. 29. The system of claim 28, wherein said transmitter further comprises (i) a CRC generator configured to generate CRC information from said transmitted data and (ii) a transmitter processor configured to append said CRC information to said transmitted data. 30. The system of claim 28, further comprising a control bus configured to transmit an indicator signal from said receiver to said transmitter, said indicator signal indicating whether there is an error in said transmitted data. 31. A network, comprising: a plurality of the systems of claim 28, in communication with each other; anda plurality of storage or communications devices, each of said storage or communications devices being in communication with one of said systems. 32. A circuit for determining a data transmission error and/or confirming an error determination, comprising: means for receiving transmitted data and error checking code calculated thereon and appended thereto, and partitioning said received data and said appended error checking code into (i) a plurality of data lines having a fixed length, and (ii) a last line containing the appended error checking code;means for performing error checking calculations on the plurality of data lines to generate an error checking result;means for selecting one of a plurality of error checking vectors, said plurality of error checking vectors comprising an initial vector, an error checking code feedback vector, and a pad vector;means for inserting said pad vector after said appended error checking code when said received data comprises a remainder, said remainder having any length less than said first fixed length and not equal to said first fixed length minus a length of said appended error checking code, said pad vector having a length providing said last line with said first fixed length when appended thereto; andmeans for indicating an error or an absence of an error in the transmitted data based on the error checking result. 33. A non-transitory computer-readable medium storing a set of instructions which, when executed by a signal processing device configured to execute computer-readable instructions, is configured to cause a receiver circuit to perform the method of claim 1. 34. The non-transitory computer-readable medium of claim 33, wherein said transmitted error checking code has a length of p bits, where p is an integer of from 8 to 128. 35. The non-transitory computer-readable medium of claim 33, wherein said fixed length comprises 2 m bits, where m is an integer of from 6 to 10. 36. The non-transitory computer-readable medium of claim 33, wherein said set of instructions further comprises an instruction to select the pad vector from a set of padding vectors. 37. The non-transitory computer-readable medium of claim 33, wherein said error checking calculations comprise cyclic redundancy check (CRC) calculations. 38. The non-transitory computer-readable medium of claim 33, wherein said predetermined state is selected from the group consisting of all zeros and all ones. 39. The non-transitory computer-readable medium of claim 33, wherein said set of instructions further comprises an instruction to indicate that there is an error in said transmitted data if said calculated error checking result does not have said predetermined state. 40. The non-transitory computer-readable medium of claim 33, wherein said set of instructions further comprises an instruction to determine a length of said remainder. 41. The non-transitory computer-readable medium of claim 40, wherein said instructions select said pad vector in response to information comprising said length of said remainder. 42. The non-transitory computer-readable medium of claim 41, wherein said pad vector is a zero-pad vector.
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