Data storage device with verify on write command
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G11C-029/00
H03M-013/00
출원번호
US-0269985
(2011-10-10)
등록번호
US-8327220
(2012-12-04)
발명자
/ 주소
Borchers, Albert T.
Swing, Andrew T.
Sprinkle, Robert S.
Klaus, Jason W.
출원인 / 주소
Google Inc.
대리인 / 주소
Brake Hughes Bellermann LLP
인용정보
피인용 횟수 :
37인용 특허 :
66
초록▼
A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a ve
A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a verify on write command from the host using the interface, write data to one of the memory devices, read the data from the memory device, calculate an error correction code for the data as the data is being read, verify the data was written correctly to the memory device using the error correction code and communicate results to the host using the interface.
대표청구항▼
1. A data storage device comprising: an interface that is arranged and configured to interface with a host;a command bus;multiple memory devices that are operably coupled to the command bus; anda controller that is operably coupled to the interface and to the command bus, wherein the controller is a
1. A data storage device comprising: an interface that is arranged and configured to interface with a host;a command bus;multiple memory devices that are operably coupled to the command bus; anda controller that is operably coupled to the interface and to the command bus, wherein the controller is arranged and configured to: receive a verify on write command from the host using the interface;responsive to the verify on write command, perform the actions of writing data to one of the memory devices, reading the data from the memory device, calculating an error correction code for the data as the data is being read, verifying the data was written correctly to the memory device using the error correction code, and communicating results to the host using the interface. 2. The data storage device of claim 1 wherein the controller is arranged and configured to calculate the error correction code without using a buffer. 3. The data storage device of claim 1 wherein the memory devices include flash memory devices. 4. The data storage device of claim 1 wherein the controller reads the data from the memory device without receiving a read command from the host. 5. The data storage device of claim 1 wherein the controller is further configured to re-write the data to a different memory location on the memory device if the error correction code indicates that the data contained errors as determined when verifying the data. 6. The data storage device of claim 1 wherein the controller is further configured to re-write the data to a same memory location on the memory device if the error correction code indicates that the data contained errors as determined when verifying the data. 7. The data storage device of claim 1 wherein the controller is configured to write data to one of the memory devices, read the data from the memory device, calculate the error correction code for the data as the data is being read and verify the data was written correctly to the memory device using the error correction code prior to communicating the results to the host. 8. A non-transitory recordable storage medium having recorded and stored thereon instructions that, when executed, perform the actions of: receiving, at a controller that is arranged and configured to control multiple memory devices, a verify on write command from a host using an interface; andresponsive to the verify on write command, performing the actions of: writing data to one of the memory devices;reading the data from the memory device;calculating an error correction code for the data as the data is being read;verifying the data was written correctly to the memory device using the error correction code; andcommunicating results to the host using the interface. 9. The recordable storage medium of claim 8 wherein the instructions that, when executed, perform the action of calculating the error correction code comprises instructions that, when executed, perform the actions of calculating the error correction code without using a buffer. 10. The recordable storage medium of claim 8 wherein the memory devices include flash memory devices. 11. The recordable storage medium of claim 8 wherein the instructions that, when executed, perform the action of reading the data from the memory device comprise instructions that, when executed, perform the action reading the data from the memory device without receiving a read command from the host. 12. The recordable storage medium of claim 8 further comprising instructions that, when executed, perform the action of re-writing the data to a different memory location on the memory device if the error correction code indicates that the data contained errors as determined when verifying the data. 13. The recordable storage medium of claim 8 further comprising instructions that, when executed, perform the action of re-writing the data to a same memory location on the memory device if the error correction code indicates that the data contained errors as determined when verifying the data. 14. The recordable storage medium of claim 8 wherein the instructions that, when executed, perform the action of writing data to one of the memory devices, reading the data from the memory device, calculating the error correction code for the data as the data is being read and verifying the data was written correctly to the memory device using the error correction code are performed prior to communicating the results to the host. 15. A method, comprising: receiving, at a controller that is arranged and configured to control multiple memory devices, a verify on write command from a host using an interface; andresponsive to the verify on write command, performing the actions of: writing data to one of the memory devices;reading the data from the memory device;calculating an error correction code for the data as the data is being read;verifying the data was written correctly to the memory device using the error correction code; andcommunicating results to the host using the interface. 16. The method as in claim 15 wherein calculating the error correction code comprises calculating the error correction code without using a buffer. 17. The method as in claim 15 wherein the memory devices include flash memory devices. 18. The method as in claim 15 wherein reading the data from the memory device reading the data from the memory device without receiving a read command from the host. 19. The method as in claim 15 further comprising re-writing the data to a different memory location on the memory device if the error correction code indicates that the data contained errors as determined when verifying the data. 20. The method as in claim 15 further comprising re-writing the data to a same memory location on the memory device if the error correction code indicates that the data contained errors as determined when verifying the data. 21. The method as in claim 15 wherein writing data to one of the memory devices, reading the data from the memory device, calculating the error correction code for the data as the data is being read and verifying the data was written correctly to the memory device using the error correction code are performed prior to communicating the results to the host.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (66)
Strecker William D. (Stow Harvard MA) Stewart Robert E. (Stow Harvard MA) Fuller Samuel (Harvard MA), Apparatus for transferring blocks of information from one node to a second node in a computer network.
Clark,Scott D.; Willenborg,Scott M., Command ordering among commands in multiple queues using hold-off vector generated from in-use vector and queue dependency scorecard.
Matsunami Naoto,JPX ; Kan Masayuki ; Kaneda Yasunori,JPX ; Yagisawa Ikuya,JPX ; Oeda Takashi,JPX ; Arakawa Hiroshi,JPX, Computer system with a reduced number of command end interrupts from auxiliary memory unit and method of reducing the nu.
Swing, Andrew T.; Sprinkle, Robert S.; Borchers, Albert T., Data storage device capable of recognizing and controlling multiple types of memory chips operating at different voltages.
Swing, Andrew T.; Borchers, Albert T.; Sprinkle, Robert S.; Klaus, Jason W.; Norrie, Thomas J.; Gelb, Benjamin S., Error correction for a data storage device.
Panner Bryan K. ; Hoskins Timothy Lee ; Napolitano Richard, File array communications interface for communicating between a host computer and an adapter.
Rubinson Barry L. (Colorado Springs CO) Gardner Edward A. (Colorado Springs CO) Grace William A. (Colorado Springs CO) Lary Richard F. (Colorado Springs CO) Keck Dale R. (Colorado Springs CO), Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems.
Short Robert T. ; Parchem John M. ; Cutler David N., Method and apparatus for reducing the rate of interrupts by generating a single interrupt for a group of events.
Wood Brian Owen, Method and computer program product for implementing multiple drag and drop operations for large objects without blocking an operating system interface.
Feeney James W. (Endicott NY) Wilhelm ; Jr. George W. (Endwell NY), Method for allowing application program in computer system to access device directly in exclusive mode by bypassing oper.
Langan John A. (Austin TX) Winter Marlan L. (Austin TX) Sibigtroth James M. (Round Rock TX), Queue system having a time-out feature and method therefor.
Satori,Kenichi; Tsutsui,Keiichi; Nakanishi,Kenichi; Bando,Hideaki; Okubo,Hideaki; Aoki,Yoshitaka; Konno,Tamaki, Storage device using interleaved memories to control power consumption.
Day, Michael Norman; Hofstee, Harm Peter; Johns, Charles Ray; Liu, Peichum Peter; Truong, Thuong Quang; Yamazaki, Takeshi, System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups.
Okin, Kenneth Alan; Moussa, George; Ganapathy, Kumar; Karamcheti, Vijay; Parekh, Rajesh, Systems and apparatus with programmable memory control for heterogeneous main memory.
Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W.; Jaser, Ihab, Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system.
Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W.; Jaser, Ihab, Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values.
Hess, Randall L.; Nash, Berck E.; Reiser, James M.; Roberson, Randy L.; Stokes, Kris B.; Yandell, Jesse L., Efficient burst data verify in shingled data storage drives.
Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab, Memory controller and integrated circuit device for correcting errors in data read from memory cells.
Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend.
Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory system with erase suspend circuit and method for erase suspend management.
Micheloni, Rino; Marelli, Alessia; Bates, Stephen, Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction.
Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab; Crippa, Luca, System and method for accumulating soft information in LDPC decoding.
Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab; Crippa, Luca, System and method for higher quality log likelihood ratios in LDPC decoding.
Borchers, Albert T.; Gelb, Benjamin S.; Norrie, Thomas J.; Swing, Andrew T., Using a logical to physical map for direct user space communication with a data storage device.
Borchers, Albert T.; Gelb, Benjamin S.; Norrie, Thomas J.; Swing, Andrew T., Using a virtual to physical map for direct user space communication with a data storage device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.