초록 ▼

An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky

An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.

대표청구항 ▼

1. An integrated circuit structure, comprising: a semiconductor substrate having a first area and two second areas separated from each other by shallow trench isolation (STI) regions;a well region of a first conductive type formed in the semiconductor substrate;a metal silicide layer formed on the w

1. An integrated circuit structure, comprising: a semiconductor substrate having a first area and two second areas separated from each other by shallow trench isolation (STI) regions;a well region of a first conductive type formed in the semiconductor substrate;a metal silicide layer formed on the well region within the first area and having an internal portion and an outer portion, wherein a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region;a guard ring of a second conductive type opposite the first conductivity type formed on the well region within the first area and encircling the metal silicide layer, wherein the outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring and the outer edge of the guard ring physically contacts the shallow trench isolation (STI) regions;two diffusion regions of the first conductive type formed in the well region within the two second areas respectively;an inter-dielectric layer formed on the shallow trench isolation region; anda conductive contact structure formed in the inter-dielectric layer and comprising a first conductive contact in physical contact with the internal portion and the outer portion of the metal silicide layer and two second conductive contacts in contact with the two diffusion regions respectively, wherein the conductive contact structure is isolated to the two diffusion regions via the inter-dielectric layer. 2. The integrated circuit structure of claim 1, wherein the first conductive contact is formed over the Schottky barrier and the inner edge of the guard ring. 3. The integrated circuit structure of claim 1, wherein the metal silicide layer comprises cobalt. 4. The integrated circuit structure of claim 1, wherein the well region is an n-type well region, and the guard ring is a p-type ring. 5. The integrated circuit structure of claim 1, further comprising a deep well region formed in the semiconductor substrate, wherein the well region is formed within the deep well region. 6. The integrated circuit structure of claim 1, wherein the metal silicide layer functions as an anode electrode of a Schottky Barrier diode, and the two diffusion regions function as two cathode electrodes of the Schottky Barrier diode. 7. The integrated circuit structure of claim 1, wherein the semiconductor substrate is a p-type silicon substrate. 8. The integrated circuit structure of claim 4, wherein the diffusion region is an n-type diffusion region having a higher impurity concentration than the n-type well region. 9. The integrated circuit structure of claim 5, wherein the deep well region is an n-type deep well region having a higher impurity concentration than the well region.