초록 ▼

A data storage system having a pair of CPU modules each one of having a port coupled to a host computer/server and a storage medium for transferring data during an IO transfer. Each one of the modules produces different types of reset signals, one of such types being a software reset signal produced

A data storage system having a pair of CPU modules each one of having a port coupled to a host computer/server and a storage medium for transferring data during an IO transfer. Each one of the modules produces different types of reset signals, one of such types being a software reset signal produced during a software upgrade of the module and other types being produced for events other than during a software upgrade, The other types produced by a first one of the modules disables the port of the first one of the modules; whereas, in response the software reset signal produced by the first one of the modules during an IO transfer, a second one of the modules couples the port of the first one of the modules to the second one of the modules to enable the IO transfer to be processed by the second one of the modules.

대표청구항 ▼

1. A data storage system comprising: a pair of CPU modules, each one of the modules having a port coupled to a host computer/server and a storage medium, for transferring user data between the host computer/server and the storage medium during an IO transfer, each one of the modules producing a plur

1. A data storage system comprising: a pair of CPU modules, each one of the modules having a port coupled to a host computer/server and a storage medium, for transferring user data between the host computer/server and the storage medium during an IO transfer, each one of the modules producing a plurality of different types of reset signals, one of such types of reset signals being a software reset signal produced during a software upgrade of the module and other types being produced for events other than during a software upgrade of the module; andwherein, said other types of the reset signals produced by a first one of the pair of modules disables the first one of the modules whereas, in response to the software reset signal produced by the first one of the modules during an IO transfer being performed by the first one of the pair of modules, a second one of the pair of modules, in response to the software reset signal produced by the first one of the pair of modules, couples the port of the first one of the pair of modules to the second one of the pair of modules to enable the IO transfer to be processed by the second one of the pair of modules; andwherein the microcontroller of the first one of the CPU modules inhibits such output reset output signal from passing to the IO controller of the first one of the CPU modules and switch of the first one of the CPU modules. 2. A data storage system having a host computer/server coupled to a storage medium, such system comprising: a pair of CPU modules, each one of the modules having a port coupled to the host computer/server and the storage medium, for transferring user data between the host computer/server and the storage medium, each one of the modules comprising: a processor complex for producing a plurality of different types of reset signals, one of such types of reset signals being a software reset signal produced during a software upgrade of the processor complex and other types of the reset signals being produced for events other than during a software upgrade of the processor complex, wherein the processor complex produces a reset output signal in response to any one of the different types of reset signals produced by the processor complex;wherein, any one of said other types of the reset signals that is produced by a first one of the pair of CPU disables the first one of the CPU modules whereas, in response to the software reset signal produced by the first one of the CPU modules during an IO transfer being performed between the host computer/server and the storage medium by a first one of the pair of CPU modules, a second one of the pair of CPU modules couples the port of the first one of the pair of CPU modules to the second one of the pair CPU modules to enable the IO transfer to be processed by the second one of the CPU modules; andwherein the microcontroller of the first one of the CPU modules inhibits such output reset output signal from passing to the IO controller of the first one of the CPU modules and switch of the first one of the CPU modules. 3. The data storage system recited in claim 2 wherein: each one of the modules comprising: an IO controller having a port connected to the host computer/server and the storage medium;a switch coupled to the IO controller, wherein the switch of one of the pair of modules is coupled to the switch of the other one of the pair of modules;a processor complex coupled to the switch;a microcontroller coupled to the processor complex;wherein, in response to any one of said other types of the reset signals the microcontroller in a first one of the pair of CPU modules enables an output reset signal produced by such first one of the CPU modules to be passed to the IO controller of the first one of the CPU modules and to the switch of the first one of the CPU modules while, in response to the software reset signal, the microcontroller of the first one of the CPU modules inhibits such output reset signal from passing to the IO controller of the first one of the CPU modules and switch of the first one of the CPU modules; andwherein, in response to the software reset signal, the microcontroller of a second one of the pair of CPU modules couples the switch of the second one of the pair of CPU modules to the IO controller of the first one of the CPU modules through the switch of the first one of the pair of CPU modules. 4. A method for operating a data storage system comprising: a pair of CPU modules each one of having a port coupled to a host computer/server and a storage medium for transferring data during an IO transfer, each one of the modules producing different types of reset signals, one of such types being a software reset signal produced during a software upgrade of the module and other types being produced for events other than during a software upgrade, the method comprising: in response to said other types being produced by a first one of the modules, the first one of the modules disables the port of the first one of the modules whereas, in response to the software reset signal produced by the first one of the modules during an IO transfer, a second one of the modules couples the port of the first one of the modules to the second one of the modules to enable the IO transfer to be processed by the second one of the modules; andwherein the microcontroller of the first one of the CPU modules inhibits such output reset output signal from passing to the IO controller of the first one of the CPU modules and switch of the first one of the CPU modules.