IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0665821
(2008-05-15)
|
등록번호 |
US-8352809
(2013-01-08)
|
우선권정보 |
DE-10 2007 028 766 (2007-06-22) |
국제출원번호 |
PCT/EP2008/055934
(2008-05-15)
|
§371/§102 date |
20091221
(20091221)
|
국제공개번호 |
WO2009/000597
(2008-12-31)
|
발명자
/ 주소 |
- Kabulepa, Lukusa Didier
- Traskov, Adrian
|
출원인 / 주소 |
- Continental Teves AG & Co. oHG
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
8 인용 특허 :
12 |
초록
▼
A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the
A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.
대표청구항
▼
1. A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the method including: generating, by the transmitter, the check data based on the serial data;combining, by the transmitter, the serial data and the generated che
1. A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the method including: generating, by the transmitter, the check data based on the serial data;combining, by the transmitter, the serial data and the generated check data to form a codeword;injecting, by the transmitter, bit errors into the codeword to generate a test word;transmitting, from the transmitter to the receiver, the test word;checking, by the receiver, the test word for bit errors by sequentially using error recognition hardware and then using error recognition software;wherein the transmitter is configured to test: i) error detection capabilities of the error recognition hardware by generating the test word such that errors in the test word are detected and corrected by the error recognition hardware to reproduce the codeword, the codeword being transmitted to the error recognition software, andii) error detection capabilities of the error recognition software by generating the test word such that errors in the test word are not detected and not corrected by the error recognition hardware, the uncorrected test word then being transmitted to the error recognition software where the errors are detected and corrected. 2. The method as claimed in claim 1, wherein a malfunction or a fault in the error recognition hardware is recognized in the receiver using the data errors or check data errors. 3. The method as claimed in claim 1, wherein the check data are formed on a basis of a CRC method. 4. The method as claimed in claim 1, wherein the errors are produced by virtue of data to be transmitted being modified by the injecting of the bit errors into the codeword. 5. The method as claimed in claim 1, wherein the error recognition software in the receiver always recognizes CRC data errors which are generated codewords with a Hamming distance below a particular threshold value. 6. An electronic system which comprises: a transmitter that generates check data based on the serial data, combines the serial data and the generated check data to form a codeword, injects bit errors into the codeword to generate a test word, and transmits the test word to a receiver that checks the test word for bit errors by sequentially using error recognition hardware and then using error recognition software,wherein the transmitter is configured to test: i) error detection capabilities of the error recognition hardware by generating the test word such that errors in the test word are detected and corrected by the error recognition hardware to reproduce the codeword, the codeword being transmitted to the error recognition software, andii) error detection capabilities of the error recognition software by generating the test word such that errors in the test word are not detected and not corrected by the error recognition hardware, the undetected test word then being transmitted to the error recognition software where the errors are detected and corrected. 7. The circuit as claimed in claim 6 further comprising transmitter-end changeover means which can be used to change over between: (a) transmitting codewords having injected errors, and (b) transmitting codewords without injected errors. 8. The circuit as claimed in claim 6, wherein the transmitter is provided with a first data conditioning stage including a first check data production circuit, which can be used to forward data and check data without errors to a transmission output, and the transmitter is provided with a second data conditioning stage having a check data production circuit, wherein each data conditioning stage can be used to produce data errors or check data errors.
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