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A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory an

A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.

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1. A memory system, comprising: a main memory comprising a plurality of single-ported memory banks, each memory bank comprising a first number of entries;parallel busses configured to enable simultaneous writing to and reading from different ones of the single-ported memory banks;a sideband memory c

1. A memory system, comprising: a main memory comprising a plurality of single-ported memory banks, each memory bank comprising a first number of entries;parallel busses configured to enable simultaneous writing to and reading from different ones of the single-ported memory banks;a sideband memory comprising the first number of entries, each of the entries in the sideband memory mapping to a corresponding one of the entries in one of the memory banks in the main memory, the sideband memory being configured to allow parallel read and write accesses to the sideband memory per cycle;switching circuitry configured to direct read and write operations to either the main memory or the sideband memory; andcontrol logic configured to track to which of the memory banks in the main memory each of the entries in the sideband memory corresponds, and to deterministically control the switching circuitry in response to memory address information to effect a pattern of access to the main memory and the sideband memory such that the memory system performs like a fully provisioned dual-ported memory, wherein when a read operation and a write operation simultaneous with the read operation are both directed to entries in a first one of the single-ported memory banks in the main memory that are not present in the sideband memory, the control logic is further configured to direct the read operation to the first single-ported memory bank in the main memory and the write operation to the sideband memory. 2. The memory system of claim 1 wherein each of the memory banks in the main memory comprises a plurality of single-ported six transistor (6T) static random access memory (SRAM) cells. 3. The memory system of claim 1 wherein the sideband memory comprises a dual-ported array. 4. The memory system of claim 3 wherein the dual-ported array comprises a plurality of dual-ported static random access memory (SRAM) cells, wherein the SRAM cells are either ten transistor (10T) SRAM cells or eight transistor (8T) SRAM cells. 5. The memory system of claim 1 wherein the sideband memory comprises first and second single-ported arrays in parallel, each of the arrays having the first number of entries, both of each corresponding pair of entries in the first and second single-ported arrays mapping to the corresponding one of the entries in one of the memory banks in the main memory, only one of each corresponding pair of entries in the first and second single-ported arrays being valid, the control logic further being configured to track which of each corresponding pair of entries is valid. 6. The memory system of claim 5 wherein the control logic comprises a tags memory that identifies the memory bank in the main memory to which each pair of corresponding entries in the sideband memory corresponds, the tags memory further identifying which of each corresponding pair of entries is valid. 7. The memory system of claim 1 wherein the control logic comprises a tags memory that identifies the memory bank in the main memory to which each of the entries in the sideband memory corresponds, the tags memory being configured to allow three memory accesses to the tags memory per cycle. 8. The memory system of claim 7 wherein the tags memory comprises a triple-ported array. 9. The memory system of claim 7 wherein the tags memory comprises first and second dual-ported arrays in parallel, each of the arrays having the first number of entries, wherein write operations to the tags memory write the same value to both of each corresponding pair of entries in the first and second dual-ported arrays, and wherein first and second simultaneous read operations read from the first and second dual-ported arrays, respectively. 10. A shared-memory switch, comprising: a plurality of receive ports;a plurality of transmit ports;a memory system comprising: a main memory comprising a plurality of single-ported memory banks, each memory bank comprising a first number of entries;parallel busses configured to enable simultaneous writing and reading from different ones of the single-ported memory banks;a sideband memory comprising the first number of entries, each of the entries in the sideband memory mapping to a corresponding one of the entries in one of the memory banks in the main memory, the sideband memory being configured to allow parallel read and write accesses to the sideband memory per cycle;switching circuitry configured to direct read and write operations to either the main memory or the sideband memory; andcontrol logic configured to track to which of the memory banks in the main memory each of the entries in the sideband memory corresponds, and to deterministically control the switching circuitry in response to memory address information to effect a pattern of access to the main memory and the sideband memory such that the memory system performs like a fully provisioned dual-ported memory, wherein when a read operation and a write operation simultaneous with the read operation are both directed to entries in a first one of the single-ported memory banks in the main memory that are not present in the sideband memory, the control logic is further configured to direct the read operation to the first single-ported memory bank in the main memory and the write operation to the sideband memory;receive crossbar circuitry operable to connect any of the receive ports with the memory system;transmit crossbar circuitry operable to connect the memory system with any of the transmit ports; andswitching logic which is operable to control interaction of the receive and transmit ports, the receive and transmit crossbar circuitry, and the memory system to effect storage and retrieval of data in the memory system.