Method and system for open loop compensation of delay variations in a delay line
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-017/14
H03K-003/011
출원번호
US-0059911
(2009-05-08)
등록번호
US-8390356
(2013-03-05)
우선권정보
IN-986/MUM/2008 (2008-05-08)
국제출원번호
PCT/IN2009/000273
(2009-05-08)
§371/§102 date
20110218
(20110218)
국제공개번호
WO2010/079503
(2010-07-15)
발명자
/ 주소
Shinde, Suhas Vishwasrao
출원인 / 주소
KPIT Cummins Infosystems, Ltd.
인용정보
피인용 횟수 :
2인용 특허 :
8
초록▼
The present invention provides a method and system for open loop compensation of delay variations in a delay line. The method includes sensing the Process, Voltage, Temperature (PVT) variations in the delay line using a sensing circuit. A first and second sensitive current are generated based on the
The present invention provides a method and system for open loop compensation of delay variations in a delay line. The method includes sensing the Process, Voltage, Temperature (PVT) variations in the delay line using a sensing circuit. A first and second sensitive current are generated based on the PVT variations. The first and second sensitive currents are mirrored currents from the sensing circuit. Then, a first compensation current is generated based on the first sensitive current and a first summing current. The first summing current is a reference current independent of the PVT variations. Further, the first compensation current is mirrored as a second summing current and a second compensation current is generated from the second sensitive current and the second summing current. The second compensation current compensates the delay variations and has a sensitivity based on the sensitivities of the first and second sensitive currents.
대표청구항▼
1. A delay compensation device comprising: a sensing unit for sensing process, supply voltage, and temperature (PVT) variations in a delay line;a sensitive current unit coupled to the sensing unit for generating a sensitive current based on the sensed PVT variations; anda current compensation unit c
1. A delay compensation device comprising: a sensing unit for sensing process, supply voltage, and temperature (PVT) variations in a delay line;a sensitive current unit coupled to the sensing unit for generating a sensitive current based on the sensed PVT variations; anda current compensation unit coupled to the sensitive current unit for generating a compensation current based on the sensitive current, wherein the compensation current compensates for delay variations in the delay line,wherein the sensitive current is a mirrored current from the sensing unit. 2. The device of claim 1, further comprises: a biasing unit coupled to the sensitive current unit for compensating process skew by adjusting sensitivity of the sensitive current. 3. The device of claim 1, wherein the sensing unit includes a threshold voltage sensor for sensing process and temperature variations. 4. The device of claim 3, wherein the threshold voltage sensor has non-zero sensitivity for variations in the supply voltage. 5. The device of claim 1, wherein the current compensation unit generates the compensation current by subtracting the sensitive current from a reference current. 6. The device of claim 5, wherein the reference current is generated from a constant current source, and wherein the reference current is independent of the sensed PVT variations. 7. A system comprising: a delay line unit; anda delay compensation unit coupled to the delay line unit comprising: a sensing unit for sensing process, supply voltage, and temperature (PVT) variations in the delay line unit;a sensitive current unit coupled to the sensing unit for generating a sensitive current based on the sensed PVT variations; anda current compensation unit coupled to the sensitive current unit for generating a compensation current based on the sensitive current, wherein the compensation current compensates for delay variations in the delay line unit,wherein the sensitive current is a mirrored current from the sensing unit. 8. The system of claim 7, wherein the delay compensation unit further comprises a biasing unit coupled to the sensitive current unit for compensating process skew by adjusting sensitivity of the sensitive current. 9. The system of claim 7, wherein the current compensation unit generates the compensation current by subtracting the sensitive current from a reference current. 10. The system of claim 9, wherein the reference current is generated from a constant current source, and wherein the reference current is independent of the sensed PVT variations. 11. The system of claim 7, wherein the delay line unit is a current controlled delay line unit having at least one non-inverting NP-current controlled delay element. 12. A multi-stage delay compensation device comprising: a sensing circuit for sensing process, supply voltage, and temperature (PVT) variations in a delay line; a first stage circuit coupled to the sensing circuit comprising: a first sensitive current circuit coupled to the sensing circuit for generating a first sensitive current based on the sensed PVT variations;a first current compensation circuit coupled to the first sensitive current circuit for generating a first compensation current based on the first sensitive current; anda first current mirror coupled to the first compensation circuit for generating a first summing current by mirroring the first compensation current; anda second stage circuit cascaded with the first stage circuit comprising: a second sensitive current circuit coupled to the sensing circuit for generating a second sensitive current based on the sensed PVT variations; anda second current compensation circuit coupled to the second sensitive current circuit for generating a second compensation current, wherein the second compensation current compensates for the delay variations in the delay line. 13. The device of claim 12, wherein the sensing circuit includes a threshold voltage sensor for sensing process and temperature variations. 14. The device of claim 13, wherein the threshold voltage sensor has non-zero sensitivity for variations in the supply voltage. 15. The device of claim 12, wherein the first stage circuit further comprising a first biasing circuit coupled to the first sensitive current circuit for compensating process skew by adjusting sensitivity of the first sensitive current. 16. The device of claim 15, wherein the first sensitive current is a mirrored current from the sensing circuit. 17. The device of claim 16, wherein the first current compensation circuit generates the first compensation current by subtracting the first sensitive current from a reference current. 18. The device of claim 17, wherein the reference current is generated from a constant current source, and wherein the reference current is independent of the sensed PVT variations. 19. The device of claim 15, wherein the second stage circuit further comprising a second biasing circuit coupled to the second sensitive current circuit for compensating process skew by adjusting sensitivity of the second sensitive current. 20. The device of claim 19, wherein the second sensitive current is a mirrored current from the sensing circuit. 21. The device of claim 20, wherein the second current compensation circuit generates the second compensation current by subtracting the second sensitive current from the first summing current. 22. The device of claim 12, wherein the sensing circuit includes a PMOS transistor and a NMOS transistor. 23. The device of claim 15, wherein the first sensitive current circuit, the first current compensation circuit, and the first biasing circuit each includes a PMOS transistor. 24. The device of claim 12, wherein the first current mirror includes a NMOS transistor and PMOS transistor. 25. The device of claim 19, wherein the second sensitive current circuit, the second current compensation circuit, and the second biasing circuit each includes a PMOS transistor.
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이 특허에 인용된 특허 (8)
Boerstler David William, CMOS process compensation circuit.
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