IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0861666
(2010-08-23)
|
등록번호 |
US-8404553
(2013-03-26)
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발명자
/ 주소 |
- Herner, Scott Brad
- Nazarian, Hagop
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
7 인용 특허 :
86 |
초록
▼
A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilico
A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction.
대표청구항
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1. A method of forming a non volatile memory device, comprising: providing a substrate having a surface region;forming a first dielectric material overlying the surface region of the semiconductor substrate;forming a first wiring material overlying the first dielectric material;forming a contact mat
1. A method of forming a non volatile memory device, comprising: providing a substrate having a surface region;forming a first dielectric material overlying the surface region of the semiconductor substrate;forming a first wiring material overlying the first dielectric material;forming a contact material comprising a doped polysilicon material overlying the first wiring material;forming a switching material comprising an amorphous silicon material overlying the contact material;subjecting the switching material to a first pattering and etching process, separating a first strip of switching material from a second strip of switching material, the first strip of switching material and the second strip of switching material being spatially oriented in a first direction; andsubjecting the first strip of switching material, the second strip of switching material, the contact material, and the first wiring material to a second patterning and etching process, forming at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material, the first wiring structure being extended in a second direction at an angle to the first direction. 2. The method of claim 1 further comprising: depositing a thickness of second dielectric material overlying each of the first switching element and the second switching element, the second dielectric material filling a void region caused by the first patterning and etching process and the second patterning and etching process to isolated at least the first switching element from the second switching element in the second direction;forming an opening region in a portion of the thickness of the second dielectric material to expose a surface region of each of the first switching element, the second switching element, the third switching element, and the fourth switching element;depositing a second wiring material including a conductive material overlying the second dielectric material, the conductive material filling the opening region and in contact with the switching material; andsubjecting the second wiring material to a third etching process to form a second wiring structure overlying the switching element, the second wiring structure being spatially parallel to the first direction. 3. The method of claim 1 wherein the second etching process further removes a portion of the contact material and the first wiring material to form a first wiring structure disposed in the first direction. 4. The method of claim 1 further comprises forming a third dielectric material to isolate the second wiring structure. 5. The method of claim 1 wherein the second dielectric material isolates the first switching element associated with a first switching device from a second switching element associated with a second switching device in the first direction, preventing disturb between the first switching device and the second switching device during writing, reading, or erasing. 6. The method of claim 1 wherein the substrate comprises a semiconductor substrate such as single silicon, silicon germanium, or silicon on insulator. 7. The method of claim 1 wherein the semiconductor substrate comprises one or more transistor devices formed thereon, the one or more transistor devices being operable coupled to the memory device. 8. The method of claim 1 wherein the first dielectric material comprises silicon oxide, silicon nitride, or a silicon oxide on silicon nitride on silicon oxide (ONO) stack. 9. The method of claim 1 wherein the first wiring material comprises copper, tungsten, or aluminum. 10. The method of claim 1 wherein the contact material prevents an interfacial region to form from the switching material and the first wiring material. 11. The method of claim 1 wherein the contact material is optional. 12. The method of claim 1 wherein the second dielectric material comprises silicon oxide, silicon nitride, or a silicon oxide on silicon nitride on silicon oxide (ONO) stack. 13. The method of claim 1 wherein the conductive material is selected from silver, gold, platinum, palladium, aluminum, and zinc, including combinations thereof. 14. The method of claim 1 wherein the conductor material forms a metal region comprising the conductive material in a portion of the switching material upon application of a voltage coupled to the first wiring structure or the second wiring structure. 15. The method of claim 14 wherein the voltage is a positive voltage applied to the second wiring structure with respect to the first wiring structure. 16. The method of claim 14 wherein the metal region comprises a plurality of metal particles, the metal particles includes clusters, ions, the metal region further comprises a filament structure characterized by a length and a distance between metal particles. 17. A method of forming a disturb-resistant non volatile memory device, comprising: providing a first cell and a second cell, the first cell being formed from a first wiring structure extending in a first direction and a second wiring structure extending in a second direction orthogonal to the first direction, a switching material comprising an amorphous silicon material, and a contact material comprising a p+ polysilicon material, a first switching region formed in an intersecting region between the first wiring structure and the second wiring structure, the second cell being formed from the first wiring structure, the switching material, the contact material, and a third wiring structure, the third wiring structure being parallel to the second wiring structure, a second switching region being formed in an intersecting region between the first wiring structure and the third wiring structure, at least the switching material and the contact material forming a coupling between the first cell and the second cell;eliminating the coupling by removing a portion of the switching material to form a void region between the first switching region and the second switching region; andfilling the void region using a dielectric material to electrically and physically isolate the first switching region and the second switching region. 18. The method of claim 17 wherein the first cell and the second cell are provided in an N by M interconnected crossbar array. 19. The method of claim 17 wherein the eliminating the coupling further removes a portion of the contact material to form a first void region between the first contact region and the second contact region, and filling the void region and the first void region using the dielectric material to physically isolate the first switching region and the second switching region and to physically isolate the first contact region and the second contact region.
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