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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0279561 (2011-10-24) |
등록번호 | US-8407525 (2013-03-26) |
우선권정보 | DE-101 42 894 (2001-09-03); DE-101 42 904 (2001-09-03); DE-101 44 733 (2001-09-11); DE-101 45 795 (2001-09-17); DE-101 54 259 (2001-11-05); DE-102 02 044 (2002-01-19); DE-102 02 175 (2002-01-20); DE-102 06 856 (2002-02-18); DE-102 07 226 (2002-02-21); DE-102 40 022 (2002-08-27) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 3 인용 특허 : 569 |
A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.
1. A method for debugging a runtime configuration of a first processing arrangement, the first processing arrangement including at least one register file and a plurality of arithmetic-logic-units (ALUs) that operate on complex instructions, which instructions define a simultaneous operation of the
1. A method for debugging a runtime configuration of a first processing arrangement, the first processing arrangement including at least one register file and a plurality of arithmetic-logic-units (ALUs) that operate on complex instructions, which instructions define a simultaneous operation of the plurality of ALUs, the method comprising: modifying the configuration to cause state information to be stored in a memory; andproviding the state information from the memory to a debugger for debugging the configuration based on the state information;wherein: the configuration is of at least one of a function and an interconnection of at least one of the ALUs and one or more of the at least one register file; andthe first processing arrangement is adapted to, while configured with the configuration, cyclically execute a plurality of operations. 2. The method according to claim 1, wherein the state information is transmitted responsive to at least one of a condition and a breakpoint being met. 3. The method according to claim 1, wherein the debugger is executed with a second processing arrangement separate from the first processing arrangement. 4. The method according to claim 3, wherein a simulator receives the state information. 5. The method according to claim 4, wherein, based on the state information, the simulator outputs internal processor details that are not otherwise visible. 6. The method according to claim 1, wherein a simulator receives the state information. 7. The method according to claim 6, wherein, based on the state information, the simulator outputs internal processor details that are not otherwise visible.
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