IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
|
| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0107058
(2011-05-13)
|
| 등록번호 |
US-8436449
(2013-05-07)
|
|
발명자
/ 주소 |
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| 출원인 / 주소 |
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| 대리인 / 주소 |
|
| 인용정보 |
피인용 횟수 :
0 인용 특허 :
44 |
초록
▼
A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the
A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.
대표청구항
▼
1. A chip package comprising: a circuit substrate comprising a glass substrate, a first metal interconnect at a top side of said glass substrate, and a second metal interconnect at a bottom side of said glass substrate, wherein said first metal interconnect is connected to said second metal intercon
1. A chip package comprising: a circuit substrate comprising a glass substrate, a first metal interconnect at a top side of said glass substrate, and a second metal interconnect at a bottom side of said glass substrate, wherein said first metal interconnect is connected to said second metal interconnect;a semiconductor chip over said top side of circuit substrate, wherein said semiconductor chip comprises a dielectric layer, a first metal layer, a second metal layer and a third metal layer connecting said first metal layer to said second metal layer, wherein said third metal layer is connected to said first metal layer through an opening in said dielectric layer, wherein said third metal layer is connected to said second metal layer not through any opening in said dielectric layer, wherein said first and second metal layers comprise electroplated copper, and said third metal layer comprises aluminum, wherein said first metal layer is connected to said first metal interconnect through, in sequence, said third metal layer and said second metal layer; anda solder under said second metal interconnect. 2. The chip package of claim 1, wherein said first metal interconnect is connected to said second metal interconnect through an interconnection in said glass substrate. 3. The chip package of claim 1, wherein said solder comprises silver. 4. The chip package of claim 1, wherein said dielectric layer comprises a nitride. 5. The chip package of claim 1, wherein said dielectric layer comprises an oxide. 6. The chip package of claim 1, wherein said dielectric layer comprises an oxynitride. 7. The chip package of claim 1, wherein said second metal layer further comprises a nickel layer on a surface of said electroplated copper of said second metal layer. 8. The chip package of claim 1, wherein said electroplated copper of said second metal layer has a thickness between 1 and 13 micrometers. 9. The chip package of claim 1 further comprising a wirebonded wire connecting said second metal layer to said first metal interconnect. 10. The chip package of claim 1, wherein said glass substrate has a thickness between 200 and 2,000 micrometers. 11. The chip package of claim 1, wherein said second metal layer further comprises a titanium-containing layer between said third metal layer and said electroplated copper of said second metal layer. 12. A chip package comprising: a circuit substrate comprising a glass substrate, a first metal interconnect at a top side of said glass substrate, and a second metal interconnect at a bottom side of said glass substrate, wherein said first metal interconnect is connected to said second metal interconnect;a semiconductor chip over said top side of circuit substrate, wherein said semiconductor chip comprises a passivation layer, a first metal layer and a second metal layer connected to said first metal layer through an opening in said passivation layer, wherein said passivation layer comprises a nitride, wherein said first and second metal layers comprise electroplated copper, wherein said first metal layer is connected to said first metal interconnect through said second metal layer; anda solder under said second metal interconnect. 13. The chip package of claim 12, wherein said first metal interconnect is connected to said second metal interconnect through an interconnection in said glass substrate. 14. The chip package of claim 12, wherein said solder comprises silver. 15. The chip package of claim 12, wherein said second metal layer further comprises a nickel layer on a surface of said electroplated copper of said second metal layer. 16. The chip package of claim 12, wherein said electroplated copper of said second metal layer has a thickness between 1 and 13 micrometers. 17. The chip package of claim 12 further comprising a wirebonded wire connecting said second metal layer to said first metal interconnect. 18. The chip package of claim 12, wherein said glass substrate has a thickness between 200 and 2,000 micrometers. 19. The chip package of claim 12, wherein said second metal layer further comprises a titanium-containing layer between said first metal layer and said electroplated copper of said second metal layer. 20. The chip package of claim 12, wherein said nitride has a thickness between 0.2 and 1.2 micrometers.
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