초록 ▼

A line card in a network node having a local memory coupled to a local controller and local logic circuit. The local memory in the line card stores state information for signals processed by the line card itself, as well as state information for signals processed by other line cards. The logic circu

A line card in a network node having a local memory coupled to a local controller and local logic circuit. The local memory in the line card stores state information for signals processed by the line card itself, as well as state information for signals processed by other line cards. The logic circuit and controller implement a same fault detection and signal processing algorithms as all other line cards in the group, to essentially effectuate a distributed and local hardware based control of automatic protection switching (APS) without interrupting a central processor. The line card also performs error checking and supervisory functions to ensure consistency of state among the line cards.

대표청구항 ▼

1. A network node comprising: a client interface that receives a client signal carrying data at a first rate;first and second line modules, the first line module being configured to supply a first plurality of optical signals, each having a corresponding one of a first plurality of wavelengths, to a

1. A network node comprising: a client interface that receives a client signal carrying data at a first rate;first and second line modules, the first line module being configured to supply a first plurality of optical signals, each having a corresponding one of a first plurality of wavelengths, to a first path, each of the first plurality of optical signals carrying information corresponding to one of a plurality of portions of the data, each of the first plurality of optical signals carrying the information at a second rate less than the first rate, the second line module being configured to supply a second plurality of optical signals, each having a corresponding one of a second plurality of wavelengths, to a second path, each of the second plurality of optical signals carrying the information corresponding to said one of the plurality of portions of the data, each of the second plurality of optical signals carrying the information at the second rate, the first plurality of wavelengths being different than the second plurality of wavelengths;first and second CPUs provided in the first and second line modules, respectively, the first CPU being configured to change a state of the first path from a protection state to a working state;first and second memories included in the first line module, and first and second memories provided in the second line module; anda communication bus coupled to the first and second memories in the first line module and the first and second memories in the second line module, such that first state information associated with the first path is stored in the first memory in the first line module and supplied over the communication bus to the first memory in the second line module, and second state information associated with the second path is stored in the second memory in the second line module and supplied over the communication path to the second memory in the first line module, wherein the first state information indicates that the first path is a working path, the first and second memories further store a common identifier associated with the first and second plurality of optical signals, such that, in response to a fault in the first path and based on the common identifier, the first and second CPUs cooperate to deactivate transmission of the first plurality of optical signals on the first path activate transmission of the second plurality of optical signals on the second path. 2. The network node of claim 1, wherein of the first and second memories in the first line module includes a plurality of memory portions. 3. The network node of claim 1, wherein each of the first and second memories in the first line module further includes first and second logic circuits for controlling the supplying of the first and second state information from the first and second memories, respectively. 4. The network node of claim 1, wherein the communication bus is a point-to-point bus or a point-to-multipoint bus. 5. The network node of claim 4, wherein the communication bus includes two or more point-to-point buses or two or more point-to-multipoint buses. 6. A network node comprising: a client interface that receives a client signal carrying data at a first rate;a first line module configured to supply a first plurality of optical signals, each having a corresponding one of a first plurality of wavelengths, to a first path and to generate a first state information associated with the first path, each of the first plurality of optical signals carrying information corresponding to one of a plurality of portions of the data, each of the first plurality of optical signals carrying the information at a second rate less than the first rate;first and second memories provided in the first line module;a second line module configured to supply a second plurality of optical signals, each having a corresponding one of a second plurality of wavelengths, to a second path and to generate second state information associated with the second path, the first plurality of wavelengths being different than the second plurality of wavelengths, each of the second plurality of optical signals carrying the information corresponding to said one of the plurality of portions of the data, each of the second plurality of optical signals carrying the information at the second rate;first and second memories provided in the second line module, the first memory in the first line module and the first memory in the second line module storing the first state information, the second memory in the second line module and the second memory in the second line module storing the second state information;first and second CPUs provided in the first and second line modules, respectively, such that first and second CPUs being configured to change a state of the first and second paths, respectively; anda communication bus coupled to each of the first and second line modules, wherein the first state information indicates that the first path is a working path, the first and second memories further store a common identifier associated with the first and second plurality of optical signals, such that, in response to a fault in the first path and based on the common identifier, the first and second CPUs cooperate to deactivate transmission of the first plurality of optical signals on the first path activate transmission of the second plurality of optical signals on the second path.