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According to one embodiment of a module, the module includes a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output. The chips are spaced apart from one another and have a combined width extending between an edge of a first ou

According to one embodiment of a module, the module includes a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output. The chips are spaced apart from one another and have a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips. The module further includes a plurality of capacitors coupled in parallel between ground and the common supply voltage, and a transverse electromagnetic (TEM) transmission line medium coupled to the common output of the chips and having a current flow direction perpendicular to the combined width of the chips.

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1. A module, comprising: a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output, the plurality of chips being spaced apart from one another and having a combined width extending between an edge of a first outer one of the chip

1. A module, comprising: a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output, the plurality of chips being spaced apart from one another and having a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips;a plurality of capacitors coupled in parallel between ground and the common supply voltage; anda transverse electromagnetic (TEM) transmission line medium coupled to the common output of the plurality of chips and having a current flow direction perpendicular to the combined width of the plurality of chips. 2. A module as claimed in claim 1, wherein the TEM transmission line medium is a strip line comprising a first electrically conductive strip dielectrically insulated from a second electrically conductive strip, the first electrically conductive strip being coupled to the common output of the plurality of chips and the second electrically conductive strip being coupled to ground. 3. A module as claimed in claim 1, wherein the TEM transmission line medium comprises a plurality of wires dielectrically insulated from one another, and wherein the inductance of each individual wire is greater than the combined inductance of all the wires. 4. A module as claimed in claim 1, wherein the TEM transmission line medium comprises a plurality of wires dielectrically insulated from one another, and wherein every other wire is coupled to the common output of the plurality of chips and the remaining wires are coupled to ground. 5. A module as claimed in claim 1, wherein the TEM transmission line medium is coupled to the common output of the plurality of chips via a plurality of bond wires. 6. A module as claimed in claim 1, wherein the TEM transmission line medium is directly connected to the output of each chip. 7. A module as claimed in claim 1, wherein the plurality of chips are arranged on an insulator, and wherein the TEM transmission line medium comprises a first metallization layer disposed on a first side of the insulator and connected to the common output of the plurality of chips and a second metallization layer disposed on an opposing second side of the insulator and connected to ground. 8. A module as claimed in claim 1, further comprising a plurality of power transistor chips integrated in the same module as the plurality of gate driver chips and having a common gate input coupled to the common output of the plurality of gate driver chips via the TEM transmission line medium. 9. A module as claimed in claim 8, wherein the plurality of power transistor chips have a common unpowered emitter input coupled to ground via the TEM transmission line medium. 10. A module, comprising: a plurality of power transistor chips coupled in parallel and having a common gate input, a common supply voltage and a common output, the plurality of chips being spaced apart from one another and having a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips;a plurality of capacitors coupled in parallel between ground and the common supply voltage; anda transverse electromagnetic (TEM) transmission line medium coupled to the common gate input of the plurality of chips and having a current flow direction perpendicular to the combined width of the plurality of chips. 11. A module as claimed in claim 10, wherein the TEM transmission line medium is a strip line comprising a first electrically conductive strip dielectrically insulated from a second electrically conductive strip, the first electrically conductive strip being coupled to the common gate input of the plurality of chips and the second electrically conductive strip being coupled to ground. 12. A module as claimed in claim 10, wherein the TEM transmission line medium comprises a plurality of wires dielectrically insulated from one another, and wherein the inductance of each individual wire is greater than the combined inductance of all the wires. 13. A module as claimed in claim 10, wherein the TEM transmission line medium comprises a plurality of wires dielectrically insulated from one another, and wherein every other wire is coupled to the common gate input of the plurality of chips and the remaining wires are coupled to ground. 14. A module as claimed in claim 10, wherein the TEM transmission line medium is coupled to the common gate input of the plurality of chips via a plurality of bond wires. 15. A module as claimed in claim 10, wherein the TEM transmission line medium is directly connected to the gate input of each chip. 16. A module as claimed in claim 10, wherein the plurality of chips are arranged on an insulator, and wherein the TEM transmission line medium comprises a first metallization layer disposed on a first side of the insulator and connected to the common gate input of the plurality of chips and a second metallization layer disposed on an opposing second side of the insulator and connected to ground. 17. A module as claimed in claim 10, further comprising a plurality of gate driver chips integrated in the same module as the plurality of power transistor chips, the plurality of gate driver chips having a common output coupled to the common gate input of the plurality of power transistor chips via the TEM transmission line medium. 18. A module as claimed in claim 10, wherein the plurality of chips have a common unpowered emitter input, and wherein the TEM transmission line medium comprises a first conductor coupled to the common gate input of the plurality of power transistor chips and a second conductor coupled to the common unpowered emitter input of the plurality of power transistor chips, the first and second conductors being insulated from one another. 19. A power transistor system, comprising: a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output;a first plurality of capacitors coupled in parallel between ground and the common supply voltage of the plurality of gate driver chips;a plurality of power transistor chips coupled in parallel and having a common gate input, a common supply voltage and a common output, the plurality of power transistor chips being spaced apart from one another and having a combined width extending between an edge of a first outer one of the power transistor chips and an opposing edge of a second outer one of the power transistor chips;a second plurality of capacitors coupled in parallel between ground and the common supply voltage of the plurality of power transistor chips; andat least one transverse electromagnetic (TEM) transmission line medium coupling the common gate input of the plurality of power transistor chips to the common output of the plurality of gate driver chips, and having a current flow direction perpendicular to the combined width of the plurality of power transistor chips. 20. A power transistor system according to claim 19, wherein the plurality of gate driver chips are spaced apart from one another and have a combined width extending between an edge of a first outer one of the gate driver chips and an opposing edge of a second outer one of the gate driver chips, and wherein the at least one TEM transmission line medium comprises first and second TEM transmission line media coupling the common gate input of the plurality of power transistor chips to the common output of the plurality of gate driver chips, the first TEM transmission line medium having a current flow direction perpendicular to the combined width of the plurality of power transistor chips, the second TEM transmission line medium having a current flow direction perpendicular to the combined width of the plurality of gate driver chips. 21. A power transistor system according to claim 20, further comprising a third TEM transmission line medium coupling the first TEM transmission line medium to the second TEM transmission line medium.