IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0945421
(2010-11-12)
|
등록번호 |
US-8492862
(2013-07-23)
|
우선권정보 |
JP-2009-260224 (2009-11-13) |
발명자
/ 주소 |
- Yamazaki, Shunpei
- Takayama, Toru
- Sato, Keiji
|
출원인 / 주소 |
- Semiconductor Energy Laboratory Co., Ltd.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
13 인용 특허 :
33 |
초록
▼
One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide s
One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
대표청구항
▼
1. A sputtering target comprising: a sintered body of at least one metal oxide selected from magnesium oxide, zinc oxide, aluminum oxide, gallium oxide, indium oxide, and tin oxide,wherein the sintered body is subjected to a heat treatment after washing the sintered body, andwherein a concentration
1. A sputtering target comprising: a sintered body of at least one metal oxide selected from magnesium oxide, zinc oxide, aluminum oxide, gallium oxide, indium oxide, and tin oxide,wherein the sintered body is subjected to a heat treatment after washing the sintered body, andwherein a concentration of hydrogen atoms contained in the sintered body is lower than 1×1016 atoms/cm3. 2. The sputtering target according to claim 1, wherein the sintered body is a sintered body of indium oxide, gallium oxide, and zinc oxide. 3. The sputtering target according to claim 1, further comprising a silicon oxide, wherein the silicon oxide is added to the sputtering target at 0.1 wt % to 20 wt % inclusive. 4. A transistor comprising an oxide semiconductor layer which is formed using a sputtering target, wherein the sputtering target includes at least one metal oxide selected from magnesium oxide, zinc oxide, aluminum oxide, gallium oxide, indium oxide, and tin oxide,wherein a concentration of hydrogen atoms contained in the oxide semiconductor layer is lower than 1×1016 atoms/cm3. 5. The transistor according to claim 4, wherein the oxide semiconductor layer is a mixed layer of indium oxide, gallium oxide, and zinc oxide. 6. The transistor according to claim 4, wherein the oxide semiconductor layer comprises a silicon oxide, wherein the silicon oxide is added to the sputtering target at 0.1 wt % to 20 wt % inclusive. 7. A transistor comprising: an oxide semiconductor layer which is formed using a sputtering target;a source electrode;a drain electrode;a gate electrode; anda gate insulating film,wherein the sputtering target includes at least one metal oxide selected from magnesium oxide, zinc oxide, aluminum oxide, gallium oxide, indium oxide, and tin oxide,wherein a concentration of hydrogen atoms contained in the oxide semiconductor layer is lower than 1×1016 atoms/cm3. 8. The transistor according to claim 7, wherein the oxide semiconductor layer is a mixed layer of indium oxide, gallium oxide, and zinc oxide. 9. The transistor according to claim 7, wherein the oxide semiconductor layer comprises a silicon oxide, wherein the silicon oxide is added to the sputtering target at 0.1 wt % to 20 wt % inclusive. 10. The transistor according to claim 7, wherein the gate insulating film is located over the gate electrode. 11. The transistor according to claim 7, wherein the oxide semiconductor layer includes a channel formation region, andwherein a resistance of the channel formation region is higher than that of a region which is in the oxide semiconductor layer and is overlapped with the source electrode or the drain electrode. 12. The transistor according to claim 7, wherein one of the source electrode and the drain electrode is located over the oxide semiconductor layer, andwherein the other of the source electrode and the drain electrode is located below the oxide semiconductor layer. 13. A semiconductor device comprising: a substrate;a transistor comprising an oxide semiconductor layer which is formed using a sputtering target, the transistor being over the substrate; anda wiring layer electrically connected to the transistor,wherein the sputtering target includes at least one metal oxide selected from magnesium oxide, zinc oxide, aluminum oxide, gallium oxide, indium oxide, and tin oxide,wherein a concentration of hydrogen atoms contained in the oxide semiconductor layer is lower than 1×1016 atoms/cm3. 14. The semiconductor device according to claim 13, wherein the oxide semiconductor layer is a mixed layer of indium oxide, gallium oxide, and zinc oxide. 15. The semiconductor device according to claim 13, wherein the oxide semiconductor layer comprises a silicon oxide, wherein the silicon oxide is added to the sputtering target at 0.1 wt % to 20 wt % inclusive. 16. The semiconductor device according to claim 13, wherein the transistor further comprises a gate electrode, a gate insulating film, a drain electrode, and a source electrode. 17. The semiconductor device according to claim 16, wherein the gate insulating film is located over the gate electrode. 18. The semiconductor device according to claim 16, wherein the oxide semiconductor layer includes a channel formation region, andwherein a resistance of the channel formation region is higher than that of a region which is in the oxide semiconductor layer and is overlapped with the source electrode or the drain electrode. 19. The semiconductor device according to claim 16, wherein one of the source electrode and the drain electrode is located over the oxide semiconductor layer, andwherein the other of the source electrode and the drain electrode is located below the oxide semiconductor layer. 20. The semiconductor device according to claim 19, wherein a part of the oxide semiconductor layer is sandwiched between the wiring layer and the other of the source electrode and the drain electrode.
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