[특허]Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component

Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/56
출원번호	US-0612922 (2012-09-13)
등록번호	US-8497158 (2013-07-30)
발명자 / 주소	Low, Jeffrey Khai Huat Lee, Kean Cheong
출원인 / 주소	Infineon Technologies AG
대리인 / 주소	Dicke, Billig & Czaja, PLLC
인용정보	피인용 횟수 : 0 인용 특허 : 38

초록 ▼

A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages.

대표청구항 ▼

1. A method for encapsulating electronic components comprising: providing a leadframe strip having an axis with two component positions arranged along the axis, each component position including a chip support substrate having a drain lead extending from the chip support substrate parallel to the axis and a source lead and a gate lead each extending parallel to the axis;providing a plurality of semiconductor chips, each semiconductor chip having a source electrode, a gate electrode and a drain electrode coupled together by a tie bar;mounting the plurality of semiconductor chips on respective ones of the chip support substrates;electrically connecting the gate electrode with an inner bonding area of the gate lead and the source electrode with an inner bonding area of the source lead by a plurality of bond wires;electrically connecting the drain electrode with the drain lead;encapsulating the semiconductor chips, the bond wires and the inner bonding areas of the source lead and of the gate lead in plastic material to form a component housing in each component position by a transfer mold process;wherein each component position is encapsulated at essentially the same time; andwherein a central portion of a first support bar extending parallel to the axis between the chip support substrates of the two component positions remains outside of the component housings. 2. The method for encapsulating electronic components of claim 1, further comprising: providing a mold having an upper part and a lower part;clamping the tie bars and the first support bars of each of the two component positions between the upper part and lower part of the mold such that two cavities are formed by the upper part and the lower part of the mold, and such that the chip support substrate of each of the two component positions of the unit floats in each of the cavities with a rear surface of the chip support substrate being spaced apart from a bottom surface defining the cavity by a distance. 3. The method for encapsulating electronic components of claim 2, wherein the plastic material is injected into each of the two cavities at essentially the same time. 4. The method for encapsulating electronic components of claim 1, wherein after the transfer molding process, the first support bar is cut by applying a bending stress. 5. The method for encapsulating electronic components of claim 2, wherein the chip support substrate includes a rear surface that is spaced apart from a bottom surface of the lower part of the mold defining the cavity by a distance in the range from approximately 0.3 mm to approximately 0.5 mm. 6. The method for encapsulating electronic components of claim 2, wherein the upper part and the lower part of the mold hold the chip support substrates of the two component positions of the unit in tension. 7. The method for encapsulating electronic components of claim 2, wherein each cavity has the dimensions of the component housing of a TO220 package. 8. The method for encapsulating electronic components of claim 3, wherein the mold has first and second portions corresponding to the first and second component positions, the first and second portions each have an outer side wall with three channels, the first and second portions each have an inner side wall with a channel and a through hole, the inner side walls of the first and second portions face one another; and wherein the method further includes:situating the leadframe strip between the upper and lower parts such that the drain, source and gate leads extend through the channels in the outer side walls, and the support bar extends through the channels in the inner side walls; andinjecting the plastic material into the cavities simultaneously through the through holes in the inner side walls.

이 특허에 인용된 특허 (38)

John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
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Carroll ; II Arthur E. (Raytown MO) Lewis ; Jr. Basil C. (Reading PA) Yeazel Howard T. (Leawood KS), Electronic device assembly and methods of making same.
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Ewer Peter R.,GBX ; Steers Mark,GBX, High current capacity semiconductor device housing.
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Arthur Woodworth GB; Peter R. Ewer GB; Ken Teasdale, High current capacity semiconductor device package and lead frame with large area connection posts and modified outline.
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Woodworth, Arthur; Ewer, Peter R.; Teasdale, Ken, High current capacity semiconductor device package and lead frame with large area connection posts and modified outline.
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Kato Hazime (Itami JPX), Lead frame assembly including a semiconductor device and a resistance wire.
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Fujita, Katsufusa, Lead frame having chip mounting part and leads of different thicknesses.
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Nishikawa Hideyuki,JPX, Leadframe allowing easy removal of tie bars in a resin-sealed semiconductor device.
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Chew Chee Hiong,MYX ; Chee Hin Kooi,MYX ; Embong Saat Shukri,MYX, Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe.
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Gillett, Blake A.; Crowley, Sean T.; Boland, Bradley D.; Edwards, Keith M., Making two lead surface mounting high power microleadframe semiconductor packages.
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McShane Michael B. (Austin TX) Woosley Alan H. (Austin TX) Primeaux Francis (Austin TX), Method for encapsulating semiconductor devices with package bodies.
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Tateno Kenichi (Shiga JPX) Yokozawa Masami (Kyoto JPX) Fujii Hiroyuki (Osaka JPX) Nishikawa Mikio (Kyoto JPX) Katoh Michio (Osaka JPX) Wada Fujio (Kyoto JPX), Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor.
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Spairisano Antonio P. (Palermo ITX) Cellai Marino (Agrate Brianza ITX), Method for manufacturing plastic encapsulated semiconductor devices.
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Hatakeyama Mikio (Tokyo JPX), Method for producing resin-molded semiconductor device having heat radiating plate embedded in the resin.
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Glenn,Thomas P., Method of making an integrated circuit package.
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Bailey Keith W. (Mesa AZ), Method of manufacturing a semiconductor leadframe structure.
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Chia Chok J. (Campbell CA) Lim Seng-Sooi (San Jose CA), Modified lead frame for reducing wire wash in transfer molding of IC packages.
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Lam, Allen K.; Williams, Richard K.; Choi, Alex K., Package for semiconductor die containing symmetrical lead and heat sink.
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Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
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Woodworth Arthur,GBX ; Pearson George,GBX ; Ewer Peter Richard,GBX, Plural semiconductor die housed in common package with split heat sink.
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Luo,Leeshawn; Bhalla,Anup; Lui,Sik K.; Ho,Yueh Se; Chang,Mike F.; Zhang,Xiao Tian, Power semiconductor package.
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Mangiagli Marcantonio (Acireale Ct ITX) Pogliese Rosario (Gravina Di Catania Ct ITX), Resin-encapsulated semiconductor device having improved adhesion.
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Hu, Tom; Davis, Terry W.; Bancod, Ludovico E.; Shin, Won Dai, Saw and etch singulation method for a chip package.
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Otremba, Ralf, Semiconductor component in a housing with mechanically inforcing flat conductor webs.
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Horie, Yoshitaka; Maeda, Masahide, Semiconductor device.
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Satou,Yukihiro; Hata,Toshiyuki, Semiconductor device.
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Takahashi Yasushi,JPX ; Hirashima Toshinori,JPX, Semiconductor device and method for manufacturing the same.
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Yasushi Takahashi JP; Toshinori Hirashima JP, Semiconductor device and method for manufacturing the same.
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Nakazawa, Yasutoshi, Semiconductor device and method for producing the same.
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Himeno Daichi (Kawanishi JPX) Kato Hazime (Itami JPX), Semiconductor device in a single package with high wiring density and a heat sink.
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Olsen, Dennis R.; Spanjer, Keith G., Semiconductor device including plateless package.
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Uchida, Shotaro, Semiconductor device manufacturing method and semiconductor device manufactured thereby.
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Brailey, Paul, Semiconductor package.
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Tanaka,Takekazu, Semiconductor package having encapsulated chip attached to a mounting plate.
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John K. Roberts ; Joseph S. Stam ; Spencer D. Reese ; Robert R. Turnbull, Semiconductor radiation emitter package.
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Udagawa Hisao,JPX ; Kotani Hiroshi,JPX, Surface mount TO-220 package and process for the manufacture thereof.
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Quinones,Maria Clemens Y.; Joshi,Rajeev, Surface mount multi-channel optocoupler.
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Lajza ; Jr. John J. ; Ramsey Charles R. ; Smith Robert M., Ultra mold for encapsulating very thin packages.
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Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component 원문보기

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Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component 원문보기

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