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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0614794 (2012-09-13) |
등록번호 | US-8501563 (2013-08-06) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 2 인용 특허 : 1457 |
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.
1. A method of forming a floating gate transistor, comprising: forming at least one pair of isolated diffused regions having a first doping type and a first doping level in a top surface of a substrate having a second doping type and a second doping level;forming a gate dielectric having a first thi
1. A method of forming a floating gate transistor, comprising: forming at least one pair of isolated diffused regions having a first doping type and a first doping level in a top surface of a substrate having a second doping type and a second doping level;forming a gate dielectric having a first thickness disposed above the top surface of the substrate at least between the pair of isolated diffusions;forming a plurality of isolated nucleation sites in the gate dielectric;forming a plurality of isolated nanocrystals on a top surface of the gate dielectric;forming an inter-gate dielectric having a second thickness disposed over the plurality of nanocrystals; andforming a control gate electrode disposed over the inter-gate dielectric. 2. The method of claim 1, wherein the nucleation sites in the gate dielectric are substantially all in the top quarter of the gate dielectric first thickness. 3. The method of claim 2, wherein the nucleation sites in the gate dielectric are substantially all on a top surface of the gate dielectric. 4. The method of claim 1, wherein the nucleation sites are formed by ion implantation. 5. The method of claim 4, wherein the ion implantation comprises a plasma doping operation. 6. The method of claim 4, wherein boron ions are implanted into silicon dioxide with an ion energy within a range from approximately 0.01 KeV to approximately 2.0 KeV, and with an ion dose within a range from approximately 1E11 ions/cm2 to approximately 1E14 ions/cm2. 7. The method of claim 1, wherein approximately 80% or more of the nanocrystals have diameters within a range of approximately 0.5 nanometers to approximately 5 nanometers, and are separated from each other by a separation distance within a range from approximately 0.5 nanometers to approximately 5 nanometers. 8. The method of claim 1, wherein the first doping type is a P type and the second doping type is an N type. 9. The method of claim 1, wherein the nanocrystals comprise a metal material. 10. The method of claim 1, wherein the nanocrystals comprise an insulator material. 11. The method of claim 1, wherein the nanocrystals comprise a semiconductor material. 12. The method of claim 1, wherein the nanocrystals comprise a high work function material. 13. The method of claim 1, wherein the nanocrystals comprise platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), titanium oxide (TiOx), cobalt oxide (CoOx), ruthenium oxide (RuOx), hafnium oxide (HfOx), aluminum oxide (Al2O3), tungsten oxide (WOx), titanium carbide (TiC), tantalum carbide (TaC), or tungsten carbide (WC). 14. The method of claim 1, wherein the nanocrystals comprise combinations of two or more of platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium oxide (TiOx), cobalt oxide (CoOx), ruthenium oxide (RuOx), hafnium oxide (HfOx), aluminum oxide (Al2O3), tungsten oxide (WOx), titanium carbide (TiC), tantalum carbide (TaC), or tungsten carbide (WC). 15. The method of claim 1, wherein the ion implanted includes boron, nitrogen, neon, argon, krypton, platinum, ruthenium, rhodium, palladium, titanium, zirconium, hafnium, silicon, germanium, cobalt, or tantalum. 16. A method of forming a floating gate transistor, comprising: forming at least one pair of isolated diffused regions having a first doping type and a first doping level in a top surface of a substrate having a second doping type and a second doping level, wherein a length between the two isolated diffused regions is approximately 40 nanometers and a width of the region between the two isolated diffused regions is approximately 40 nanometers forming a 40 by 40 nanometer channel region;forming a gate dielectric having a first thickness disposed above the top surface of the substrate at least between the pair of isolated diffusions;forming a plurality of isolated nucleation sites in the gate dielectric;forming isolated nanocrystals on a top surface of the gate dielectric with a substantially even statistical distribution across the channel region;forming an inter-gate dielectric having a second thickness disposed over the plurality of nanocrystals; andforming a control gate electrode disposed over the inter-gate dielectric. 17. The method of claim 16, wherein there are approximately 100 electrically isolated nanocrystals distributed substantially evenly across the channel region. 18. The method of claim 16, wherein approximately 80% or more of the nanocrystals have diameters within a range of approximately 0.5 nanometers to approximately 5 nanometers, and are separated from each other by a separation distance within a range from approximately 0.5 nanometers to approximately 5 nanometers. 19. The method of claim 16, further comprising electrically interconnecting the plurality of transistors to form a memory device. 20. A method of forming a floating gate transistor, comprising: forming at least one pair of isolated diffused regions having a first doping type and a first doping level in a top surface of a substrate having a second doping type and a second doping level;forming a gate dielectric having a first thickness disposed above the top surface of the substrate at least between the pair of isolated diffusions;performing ion implantation to form a plurality of isolated nucleation sites in the gate dielectric;forming a plurality of isolated nanocrystals on a top surface of the gate dielectric;forming an inter-gate dielectric having a second thickness disposed over the plurality of nanocrystals; andforming a control gate electrode disposed over the inter-gate dielectric. 21. The method of claim 20, wherein boron ions are implanted into silicon dioxide with an ion energy within a range from approximately 0.01 KeV to approximately 2.0 KeV, and ions are implanted with an ion dose within a range from approximately 1E11 ions/cm2 to approximately 1E14 ions/cm2. 22. The method of claim 20, wherein the nucleation sites in the gate dielectric are substantially all on a top surface of the gate dielectric. 23. The method of claim 20, wherein the ion implantation comprises a plasma doping operation. 24. The method of claim 20, wherein approximately 80% or more of the nanocrystals have diameters within a range of approximately 0.5 nanometers to approximately 5 nanometers, and are separated from each other by a separation distance within a range from approximately 0.5 nanometers to approximately 5 nanometers. 25. The method of claim 20, wherein the nanocrystals comprise a material selected from the list including platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium oxide (TiOX), cobalt oxide (CoOX), ruthenium oxide (RuOX), hafnium oxide (HfOX), aluminum oxide (Al2O3), tungsten oxide (WOX), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), and combinations thereof. 26. The method of claim 20, wherein performing ion implantation includes implanting an ion species selected from a group of ions consisting of boron, nitrogen, neon, argon, krypton, platinum, ruthenium, rhodium, palladium, titanium, zirconium, hafnium, silicon, germanium, cobalt, and tantalum.
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