[특허]Top layers of metal for high performance IC's

Megica Corporation

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특허 상세정보

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내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Top layers of metal for high performance IC's

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/29
미국특허분류(USC)	257/778; 257/691; 257/692; 257/758; 257/759; 257/760
출원번호	US-0829110 (2007-07-27)
등록번호	US-8531038 (2013-09-10)
발명자 / 주소	Lin, Mou-Shiung
출원인 / 주소	Megica Corporation
대리인 / 주소	Seyfarth Shaw LLP
인용정보	피인용 횟수 : 1 인용 특허 : 517

초록

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

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1. An integrated circuit chip comprising: a silicon substrate;multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;a first dielectric layer over said silicon substrate;a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;a second dielectric layer between said first and second metal layers;a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer;a second metallization structure over said passivation layer and on said first and second contact points, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises electroplated copper; anda first polymer layer between said third and fourth metal layers. 2. The integrated circuit chip of claim 1, wherein said second metallization structure comprises a power interconnect connecting said first contact point to said second contact point. 3. The integrated circuit chip of claim 1, wherein said second metallization structure comprises a ground interconnect connecting said first contact point to said second contact point. 4. The integrated circuit chip of claim 1, wherein said first opening has a width between 0.5 and 3 micrometers. 5. The integrated circuit chip of claim 1 further comprising a second polymer layer on said passivation layer, wherein a third opening in said second polymer layer is over said first contact point, and a fourth opening in said second polymer layer is over said second contact point, wherein said third metal layer is on said second polymer layer. 6. The integrated circuit chip of claim 5, wherein said second polymer layer has a thickness between 2 and 30 micrometers. 7. The integrated circuit chip of claim 5, wherein said second polymer layer comprises polyimide. 8. The integrated circuit chip of claim 1, wherein said nitride layer has a thickness between 0.5 and 2 micrometers. 9. The integrated circuit chip of claim 1, wherein said first polymer layer comprises polyimide. 10. The integrated circuit chip of claim 1, wherein said second metallization structure comprises a signal interconnect connecting said first contact point to said second contact point. 11. The integrated circuit chip of claim 1, wherein said passivation layer further comprises an oxide layer under said nitride layer. 12. An integrated circuit chip comprising: a silicon substrate;multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;a first dielectric layer over said silicon substrate;a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;a second dielectric layer between said first and second metal layers;a separating layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said separating layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers;a second metallization structure over said passivation layer and on said first and second contact points, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises electroplated copper; anda first polymer layer between said third and fourth metal layers. 13. The integrated circuit chip of claim 12, wherein said first opening has a width between 0.5 and 3 micrometers. 14. The integrated circuit chip of claim 12, wherein said second metallization structure comprises a power interconnect connecting said first contact point to said second contact point. 15. The integrated circuit chip of claim 12, wherein said second metallization structure comprises a ground interconnect connecting said first contact point to said second contact point. 16. The integrated circuit chip of claim 12 further comprising a second polymer layer on said separating layer, wherein a third opening in said second polymer layer is over said first contact point, and a fourth opening in said second polymer layer is over said second contact point, wherein said third metal layer is on said second polymer layer. 17. The integrated circuit chip of claim 16, wherein said second polymer layer has a thickness between 2 and 30 micrometers. 18. The integrated circuit chip of claim 16, wherein said second polymer layer comprises polyimide. 19. The integrated circuit chip of claim 12, wherein said first polymer layer comprises polyimide. 20. An integrated circuit chip comprising: a silicon substrate;multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;a first dielectric layer over said silicon substrate;a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a topmost sub-micron integrated circuit of said integrated circuit chip;a second dielectric layer between said first and second metal layers;a separating layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said separating layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said first opening has a width between 0.5 and 3 micrometers;a second metallization structure over said separating layer and on said first and second contact points, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises electroplated copper; anda polymer layer between said third and fourth metal layers. 21. The integrated circuit chip of claim 20, wherein said separating layer comprises a nitride layer. 22. The integrated circuit chip of claim 20, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers. 23. The integrated circuit chip of claim 20, wherein said separating layer comprises an oxide layer. 24. The integrated circuit chip of claim 20, wherein said separating layer comprises an oxide layer having a thickness between 0.15 and 2 micrometers. 25. The integrated circuit chip of claim 1, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point. 26. The integrated circuit chip of claim 12, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point. 27. The integrated circuit chip of claim 20, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.

이 특허에 인용된 특허 (517)

이 특허를 인용한 특허 피인용횟수: 1

Suzuki, Takashi. Semiconductor device including wiring having main portion and extended portion. USP2014078786086.

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