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A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the co

A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

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1. A Low Density Parity Check (LDPC) encoder comprising: a memory module including at least N×L×K storage locations, where N and L are positive integers and K is an integer >1;a controllable permuter for performing element re-ordering operations on at least N elements coupled to said memory module;a

1. A Low Density Parity Check (LDPC) encoder comprising: a memory module including at least N×L×K storage locations, where N and L are positive integers and K is an integer >1;a controllable permuter for performing element re-ordering operations on at least N elements coupled to said memory module;a vector accumulator module including N accumulators arranged in parallel, said vector accumulator module including: i) a first input at least N bits wide corresponding to an output of said controllable permuter,ii) a second input at least N bits wide, andiii) a vector accumulator output at least N bits wide;a controllable storage device including N×K storage locations, said controllable storage device including a block select control signal input for receiving a signal indicating a block of at least N storage locations to be accessed and a storage device output at least N bits wide for outputting values read from said storage devices; anda block selection module coupled to said controllable storage device for supplying a block selection control signal to said controllable storage device. 2. The encoder of claim 1, further comprising: a control module for generating a first selection module control signal as a function of the encoding operation to be performed, said first selection module control signal being supplied as a first control signal input to said block selection module. 3. The encoder of claim 2, wherein said block selection module generates said block selection control signal as a function of a code lifting factor; andwherein said control module further generates a re-ordering control signal supplied to a reordering control input of said permuter module. 4. The encoder of claim 2, further comprising: a bus, at least N bits wide, for coupling said memory module to said controllable permuter. 5. The encoder of claim 3, wherein said block selection module further includes a block address select output coupled to a corresponding input of said memory module. 6. The encoder of claim 3, wherein said block selection module further includes a second selection module control input for receiving a signal indicating a code lifting factor to be used. 7. The encoder of claim 6, wherein said control module further generates a memory address control signal which is supplied to said memory module. 8. The encoder of claim 7, wherein said memory module includes addressing logic for generating a memory access signal from said memory address control signal and said block address select signal. 9. The encoder of claim 8, wherein said controllable storage device further includes a read/write control input; andwherein the control module further comprises a read/write control signal output coupled to the read/write control input of said controllable storage device. 10. The encoder of claim 1, wherein the storage device output of said controllable storage device is coupled to said second input of said vector accumulator module and an input of said memory module. 11. The encoder of claim 9, wherein said read/write control signal output is further coupled to a corresponding input of said memory module. 12. The encoder of claim 7, wherein the memory address control signal is an integer value greater than 0 and less than L+1 and cycles through each represented integer value 1 through L during an encoding operation, where L is a positive integer. 13. The encoder of claim 6, wherein the code lifting factor to be used is a user selected control value SK which is a factor of K. 14. The encoder of claim 13, wherein when the code lifting factor SK is less than K, N×L×(K−SK) storage locations in said memory module are left unused during the encoding. 15. The encoder of claim 13, wherein when the code lifting factor SK is less than K, a portion of said N×K storage locations in said controllable storage device are left unused during the encoding. 16. The encoder of claim 1, wherein each of the N×L×K storage locations in said memory module is a one bit storage location; andwherein each of the N×K storage locations in said controllable storage device is a one bit storage location. 17. The encoder of claim 1, wherein said control module includes a set of microcode instructions which are descriptive of the code structure to be used for encoding data, each microcode instruction corresponding to a code structure being executed K times to encode a codeword having a total length of K×N×L bits. 18. A method of performing Low Density Parity Check (LDPC) encoding processing comprising: providing an encoder including: a memory module including N×L×K storage locations, where N and L are positive integers and K is an integer >1;a controllable permuter for performing element re-ordering operations on at least N elements coupled to said memory module;a vector accumulator module including N accumulators arranged in parallel, said vector accumulator module including: i) a first input at least N bits wide corresponding to an output of said controllable permuter,ii) a second input at least N bits wide, andiii) a vector accumulator output at least N bits wide;a controllable storage device including N×K storage locations, said controllable storage device including a block select control signal input for receiving a signal indicating a block of at least N storage locations to be accessed and a storage device output at least N bits wide for outputting values read from said storage devices;a code lifting based block selection module coupled to said controllable storage device for supplying a block selection control signal to said controllable storage device;generating a first selection module control signal as a function of a stored code description and a clock signal used to control the timing of encoding operations;supplying said first selection module control signal to said code lifting based block select module; andoperating the code lifting based block selection module to select a block of memory locations to be accessed in said controllable storage device as a function for said first selection module control signal. 19. The method of claim 18, further comprising: generating a re-ordering control signal;supplying the reordering control signal to said permuter module; andoperating the permuter module to perform a message reordering operation in accordance with said supplied reordering control signal. 20. The method of claim 19, further comprising: operating said code lifting based block selection module to generate a block address select signal as a function stored code description information; andsupplying said block address select signal to said memory module for use in determining a set of memory locations to be accessed. 21. The method of claim 19, further comprising: operating said code lifting based block selection module to receive a signal indicating a code lifting factor to be used. 22. The method of claim 21, further comprising: operating said control module to generate a memory address control signal to be used in determining the set of memory locations to be accessed; andsupplying said memory address control signal to said memory module. 23. The method of claim 22, wherein said memory module includes an addressing module, the method further comprising: operating said addressing module to generate a memory access signal from said memory address control signal and said block address select signal, the memory access signal control which particular block of memory locations is accessed at a point in time. 24. The method of claim 23, further comprising: operating the control module to generate a read/write control signal used to control whether a controllable storage access operation is to be a read or a write access operation; andsupplying the generated read/write control signal to the controllable storage device. 25. The method of claim 22, wherein the memory address control signal is an integer value greater than 0 and less than L+1, the method further comprising: cycling through each represented integer value 1 through L while encoding a set of bits. 26. The method of claim 21, wherein the code lifting factor to be used is a user selected value SK which is a factor of K. 27. The method of claim 26, further comprising: leaving some of said N×L×K storage locations in said memory module unused during encoding when the code lifting factor SK is an integer less than K. 28. The method of claim 27, wherein each of the N×L×K storage locations in said memory module is a one bit storage location, and wherein leaving some of said N×L×K storage locations unused includes leaving K−SK storage locations unused. 29. The method of claim 26, further comprising: leaving some of said N×K storage locations in said controllable storage device are left unused during the encoding when the code lifting factor SK is less than K. 30. The method of claim 29, wherein each of the N×K storage locations in said controllable storage device is a one bit storage location and where leaving some of said N×K storage locations in said controllable storage device unused during the encoding includes leaving K−SK storage locations unused. 31. A Low Density Parity Check (LDPC) encoder comprising: memory means for storing, said memory means including at least N×L×K storage locations, where N and L are positive integers and K is an integer >1;controllable permuter means for performing element re-ordering operations on at least N elements coupled to said memory means;vector accumulator means including N accumulators arranged in parallel, said vector accumulator means including: i) a first input at least N bits wide corresponding to an output of said controllable permuter,ii) a second input at least N bits wide, andiii) a vector accumulator output at least N bits wide;controllable storage means including N×K storage locations, said controllable storage means including a block select control signal input for receiving a signal indicating a block of at least N storage locations to be accessed and a storage means output at least N bits wide for outputting values read from said storage means; andblock selection means coupled to said controllable storage means, for supplying a block selection control signal to said controllable storage means. 32. The encoder of claim 31, further comprising: control means for generating a first selection control signal as a function of the encoding operation to be performed, said first selection control signal being supplied as a first control signal input to said block selection means. 33. A computer program product for controlling an encoder to implement a method of performing Low Density Parity Check (LDPC) encoding operations, said encoder including a memory module including N×L×K storage locations, where N and L are positive integers and K is an integer >1, a controllable permuter, a vector accumulator module, a controllable storage device including N×K storage locations, a code lifting based block selection module for supplying a block selection control signal to said controllable storage device, the computer program product comprising: a computer-readable medium comprising:code for controlling generation of a first selection module control signal as a function of a stored code description and a clock signal used to control the timing of encoding operations;code for controlling said first selection module control signal to be supplied to said code lifting based block select module; andcode for controlling the code lifting based block selection module to select a block of memory locations to be accessed in said controllable storage device as a function for said first selection module control signal. 34. A processor for performing Low Density Parity Check (LDPC) encoding operations, said processor including an encoder which includes a memory module including N×L×K storage locations, where N and L are positive integers and K is an integer >1, a controllable permuter, a vector accumulator module, a controllable storage device including N×K storage locations, a code lifting based block selection module for supplying a block selection control signal to said controllable storage device, said processor being configured to: generate a first selection module control signal as a function of a stored code description and a clock signal used to control the timing of encoding operations;supply said first selection module control signal to said code lifting based block select module; andoperate the code lifting based block selection module to select a block of memory locations to be accessed in said controllable storage device as a function for said first selection module control signal. 35. The processor of claim 34, wherein the processor is further configured to: generate a re-ordering control signal;supply the reordering control signal to said permuter module; andoperate the permuter module to perform a message reordering operation in accordance with said supplied reordering control signal. 36. A method of performing Low Density Parity Check (LDPC) encoding processing comprising: providing an encoder including: a memory module including N×L×K storage locations, where N and L are positive integers and K is an integer >1;a controllable permuter for performing element re-ordering operations on at least N elements coupled to said memory module;a vector accumulator module including N accumulators arranged in parallel, said vector accumulator module including: i) a first input at least N bits wide corresponding to an output of said controllable permuter,ii) a second input at least N bits wide, andiii) a vector accumulator output at least N bits wide;a controllable storage device including N×K storage locations, said controllable storage device including a block select control signal input for receiving a signal indicating a block of at least N storage locations to be accessed and a storage device output at least N bits wide for outputting values read from said storage devices; anda block selection module coupled to said controllable storage device for supplying a block selection control signal to said controllable storage device. 37. The method of claim 36, further comprising: generating a first selection module control signal as a function of a stored code description and a clock signal used to control the timing of encoding operations;supplying said first selection module control signal to said block select module, wherein said block select module is a code lifting based block selection module; andoperating the code lifting based block selection module to select a block of memory locations to be accessed in said controllable storage device as a function for said first selection module control signal. 38. The method of claim 36, further comprising: generating a re-ordering control signal;supplying the reordering control signal to said permuter module; andoperating the permuter module to perform a message reordering operation in accordance with said supplied reordering control signal. 39. The method of claim 38, further comprising: operating said code lifting based block selection module to generate a block address select signal as a function stored code description information; andsupplying said block address select signal to said memory module for use in determining a set of memory locations to be accessed. 40. The method of claim 38, further comprising: operating said code lifting based block selection module to receive a signal indicating a code lifting factor to be used. 41. The method of claim 40, further comprising: operating said control module to generate a memory address control signal to be used in determining the set of memory locations to be accessed; andsupplying said memory address control signal to said memory module. 42. The method of claim 41, wherein said memory module includes an addressing module, the method further comprising: operating said addressing module to generate a memory access signal from said memory address control signal and said block address select signal, the memory access signal control which particular block of memory locations is accessed at a point in time. 43. The method of claim 42, further comprising: operating the control module to generate a read/write control signal used to control whether a controllable storage access operation is to be a read or a write access operation; andsupplying the generated read/write control signal to the controllable storage device. 44. The method of claim 41, wherein the memory address control signal is an integer value greater than 0 and less than L+1, the method further comprising: cycling through each represented integer value 1 through L while encoding a set of bits. 45. The method of claim 41, wherein the code lifting factor to be used is a user selected value SK which is a factor of K. 46. The method of claim 45, further comprising: leaving some of said N×L×K storage locations in said memory module unused during encoding when the code lifting factor SK is an integer less than K. 47. The method of claim 46, wherein each of the N×L×K storage locations in said memory module is a one bit storage location, and wherein leaving some of said N×L×K storage locations unused includes leaving K−SK storage locations unused. 48. The method of claim 47, further comprising: leaving some of said N×K storage locations in said controllable storage device are left unused during the encoding when the code lifting factor SK is less than K. 49. The method of claim 48, wherein each of the N×K storage locations in said controllable storage device is a one bit storage location and where leaving some of said N×K storage locations in said controllable storage device unused during the encoding includes leaving K−SK storage locations unused.