Load shedding during emergency power off event
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-011/30
G06F-001/00
출원번호
US-0725844
(2010-03-17)
등록번호
US-8539274
(2013-09-17)
발명자
/ 주소
Atkins, Robert G.
Cohen, Edward N.
Corcoran, Philip M.
Petrowsky, William J.
Seminaro, Edward J.
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Jung, Dennis
인용정보
피인용 횟수 :
1인용 특허 :
17
초록▼
A method, apparatus, and computer program product for load shedding during an emergency power off event. In one embodiment, power is supplied from a main power source to a plurality of electrical loads within a device enclosure. Power loss is detected from the main power source. Upon detecting the p
A method, apparatus, and computer program product for load shedding during an emergency power off event. In one embodiment, power is supplied from a main power source to a plurality of electrical loads within a device enclosure. Power loss is detected from the main power source. Upon detecting the power loss, at least one of the electrical loads is disconnected from a supplemental power source such that power to at least one remaining load connected to the supplemental power source is sustained by the supplementary power source.
대표청구항▼
1. A method comprising: supplying power from a main power source to a plurality of electrical loads within a device enclosure;detecting a power loss from the main power source;upon detecting the power loss, disconnecting at least one of the electrical loads from a supplemental power source such that
1. A method comprising: supplying power from a main power source to a plurality of electrical loads within a device enclosure;detecting a power loss from the main power source;upon detecting the power loss, disconnecting at least one of the electrical loads from a supplemental power source such that power to at least one remaining load connected to the supplemental power source is sustained by the supplemental power source; andupon detecting the power loss, sending a power loss warning to the at least one remaining load. 2. The method of claim 1, further comprising energizing the supplemental power source within the device enclosure. 3. The method of claim 1, further comprising, upon detecting the power loss, disconnecting at least one of the electrical loads from the main power source. 4. The method of claim 1, further comprising, upon detecting the power loss, transferring data from a volatile memory to a non-volatile memory by the at least one remaining load. 5. The method of claim 1, further comprising, upon detecting the power loss, completing one or more open transactions by the at least one remaining load. 6. The method of claim 1, further comprising, upon detecting the power loss, transmitting an emergency signal by the at least one remaining load. 7. The method of claim 1, wherein detecting the power loss includes detecting that an output voltage from the main power source is below a threshold value. 8. An apparatus comprising: a main power supply within a device enclosure;a supplemental power supply within the device enclosure electrically coupled with the main power supply;a soft switch configured to disconnect at least one secondary device from the supplemental power supply upon power loss from the main power supply such that power to at least one primary device connected to the supplemental power supply is sustained by the supplemental power supply,a detection circuit coupled to the main power supply, the detection circuit configured to detect the power loss from the main power supply;a management processor coupled to the detection circuit and the soft switch; andwherein, upon detection of the power loss by the detection circuit, the management processor is configured to output a power loss warning to the at least one remaining load. 9. The apparatus of claim 8, wherein the supplemental power supply is electrically coupled with the main power supply in parallel circuit. 10. The apparatus of claim 8, wherein the supplemental power supply is a holdup capacitor. 11. The apparatus of claim 8, wherein the supplemental power supply includes a battery. 12. The apparatus of claim 8, wherein the at least one primary device is a hard drive. 13. The apparatus of claim 8, wherein the at least one primary device is a hard drive array. 14. The apparatus of claim 8, wherein the at least one secondary device is a fan. 15. The apparatus of claim 8, wherein the soft switch is a transistor. 16. A computer program product comprising: a non-transitory computer readable storage medium having computer readable program code embodied therewith, the computer readable program code configured to:receive a power loss signal from a power loss detection circuit indicating a power loss from a main power source;upon receipt of the power loss signal, transmit a soft switch signal to a soft switch to disconnect at least one electrical load from a supplemental power source such that power to at least one remaining load connected to the supplemental power source is sustained by the supplemental power source; andupon receipt of the power loss signal, transmit a power loss warning to the at least one remaining load.
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이 특허에 인용된 특허 (17)
Hawley George T. (Santa Clara CA), Apparatus and method for monitoring power loss in a telecommunications system.
Manuell,Jeffrey Donald; Pascoe,Michael James; Peters,Maureen Faye, Automated load shedding of powered devices in a computer complex in the event of utility interruption.
Marrington S. Paul (P.O. Box 34 Fyshwick CA AUX 2609) Kiankhooy-Fard Paul (1165 Archer St. San Diego CA 92109) Zecos Paul (13367 Caminito Mar Villa Del Mar CA) Rudaw Geoffrey (43 Argow Pl. Nanuet NY , Computer power system.
Young Glenn S. (Lee\s Summit MO) Laudel ; Jr. Arthur (Leawood KS), Method and apparatus for controlling loads in electric power systems by reduction of peak loads.
Hammer Jeffrey M. (New Brighton MN) Ullestad David C. (St. Louis Park MN) Wesoloski Stephen J. (Eagan MN), Method and apparatus for power load shedding.
Sullivan,Douglas; Sharma,Navin, System, method and apparatus for controlling supply of backup power to first and second power planes in the event of a power failure of a main power supply.
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