Virtual devices using a plurality of processors
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/46
G06F-013/00
G06F-015/173
출원번호
US-0049179
(2008-03-14)
등록번호
US-8549521
(2013-10-01)
발명자
/ 주소
Brokenshire, Daniel Alan
Day, Michael Norman
Minor, Barry L
Nutter, Mark Richard
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
VanLeeuwen & VanLeeuwen
인용정보
피인용 횟수 :
3인용 특허 :
97
초록▼
An approach is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU c
An approach is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU can be programmed to perform several functions on behalf of the other processors in the system. The application, preferably running in one of the primary (PU) processors, issues IOCTL commands through device drivers that correspond to SPUs. The kernel managing the primary processors responds by sending an appropriate message to the SPU that is performing the dedicated function. Using this method, an SPU can be virtualized for swapping multiple tasks or dedicated to performing a particular task.
대표청구항▼
1. A computer-implemented method for using a processor as a virtual device, said method comprising: loading data, by a first processor, to a first location in a common memory, wherein the common memory is shared by a plurality of heterogeneous processors in a computer system;writing an instruction b
1. A computer-implemented method for using a processor as a virtual device, said method comprising: loading data, by a first processor, to a first location in a common memory, wherein the common memory is shared by a plurality of heterogeneous processors in a computer system;writing an instruction block, by the first processor, to a second location in the common memory, the instruction block identifying the first location and a third location in the common memory, the third location corresponding to software code that is configured to process the data;writing, by the first processor, the second location to a mailbox corresponding to a second processor from the plurality of heterogeneous processors in the computer system;retrieving the instruction block, by the second processor, from the common memory in response to the first processor writing the second location to the mailbox;storing the data, by the second processor, in a local memory corresponding to the second processor in response to retrieving the instruction block;loading the software code, by the second processor, from the third location in the common memory to the second processor's local memory; andprocessing the data by the second processor using the software code loaded in the second processor's local memory. 2. The method as described in claim 1 further comprising: writing, from a software program executing on the first processor, the data into an input buffer stored in the common memory, wherein the storing further includes sending the data from the input buffer into the second processor's local memory. 3. The method as described in claim 2 wherein the sending of the data into the second processor's local memory and the loading of the software code are both performed using DMA operations. 4. The method as described in claim 3 wherein the DMA operations are performed using one of a plurality of DMA controllers, one of which being assigned to the first processor and a second of which being assigned to the second processor. 5. The method as described in claim 1 further comprising: generating result data, stored in the second processor's local memory, in response to the processing. 6. The method as described in claim 5 further comprising: writing the result data to an output buffer stored in the common memory. 7. The method as described in claim 5 further comprising: writing the result data to an input buffer located in another device. 8. The method as described in claim 7 further comprising: signaling, from the second processor, a third processor from the plurality of heterogeneous processors, wherein the third processor includes a different local memory;storing the result data in the third processor's different local memory; andprocessing the result data by the third processor using other software code stored in the third processor's different local memory. 9. The method as described in claim 5 further comprising: writing the result data to a physical device. 10. The method as described in claim 1 wherein the software code stored in the second processor's local memory includes a plurality of code routines, the method further comprising: identifying one of the code routines based upon the request; andexecuting the identified code routine. 11. The method as described in claim 1 further comprising: initializing a task queue for one or more device functions to be performed by one or more of the plurality of heterogeneous processors, wherein the method further comprises:writing the request to the task queue;determining, by the second processor, that the request is in the task queue; andreading the request from the task queue in response to the determination. 12. The method as described in claim 1 further comprising: reading, by the second processor, the second location from the second processor's mailbox;reading, by the second processor, the first and third locations from the instruction block stored at the second location; andreading, by the second processor, the data from the first location in the common memory prior to storing the data in the second processor's local memory. 13. The method as described in claim 1 further comprising: reading, by the second processor, the software code stored at the third location in the common memory. 14. The method as described in claim 13 wherein the reading and loading of the software code are performed in response to determining that the software code stored at the third location in the common memory is not already stored in the second processor's local memory. 15. An information handling system comprising: a plurality of heterogeneous processors;a common memory shared by the plurality of heterogeneous processors;a first processor selected from the plurality of heterogeneous processors that sends a request to a second processor, the second processor also being selected from the plurality of heterogeneous processors;a local memory corresponding to the second processor;a DMA controller associated with the second processor, the DMA controller configured to transfer data between the common memory and the second processor's local memory; anda virtual device tool for operating the second processor as a virtual device, the virtual device tool including software effective to: load data, by the first processor, to a first location in the common memory;write an instruction block, by the first processor, to a second location in the common memory, the instruction block identifying the first location and a third location in the common memory, the third location corresponding to software code that is configured to process the data;write the second location, by the first processor, to a mailbox corresponding to the second processor;retrieve the instruction block, by the second processor, from the common memory in response to the first processor writing the second location to the mailbox;store the data, by the second processor, in a local memory corresponding to the second processor in response to retrieving the instruction block;load the software code, by the second processor, from the third location in the common memory to the second processor's local memory; andprocess the data by the second processor using the software code loaded in the second processor's local memory. 16. The information handling system as described in claim 15 further comprising software effective to: write, from a software program executing on the first processor, the data into an input buffer stored in the common memory, wherein the storing further includes sending the data from the input buffer into the second processor's local memory. 17. The information handling system as described in claim 16 wherein the sending of the data into the second processor's local memory and the loading of the software code are both performed using DMA operations with the DMA controller. 18. The information handling system as described in claim 15 further comprising software effective to: generate result data, stored in the second processor's local memory, in response to processing the data using the software code. 19. The information handling system as described in claim 18 further comprising software effective to: write the result data to an output buffer stored in the common memory. 20. The information handling system as described in claim 18 further comprising software effective to: write the result data to an input buffer located in another device. 21. The information handling system as described in claim 20 further comprising software effective to: signal, from the second processor, a third processor from the plurality of heterogeneous processors, wherein the third processor includes a different local memory;store the result data in the third processor's different local memory; andprocess the result data by the third processor using other software code stored in the third processor's different local memory. 22. The information handling system as described in claim 18 further comprising software effective to: write the result data to a physical device. 23. The information handling system as described in claim 15 wherein the software code stored in the second processor's local memory includes a plurality of code routines, the information handling system further comprising software effective to: identify one of the code routines based upon the request; andexecute the identified code routine. 24. The information handling system as described in claim 15 further comprising software effective to: initialize a task queue for one or more device functions to be performed by one or more of the plurality of heterogeneous processors, wherein the information handling system further includes software effective to:write the request to the task queue;determine, by the second processor, that the request is in the task queue; andread the request from the task queue in response to the determination. 25. The information handling system as described in claim 15 further comprising software to: read, by the second processor, the second location from the second processor's mailbox;read, by the second processor, the first and third locations from the instruction block stored at the second location; andread, by the second processor, the data from the first location in the common memory prior to storing the data in the second processor's local memory. 26. The information handling system as described in claim 15 further comprising software effective to: read, by the second processor, the software code stored at the third location in the common memory. 27. The information handling system as described in claim 26 wherein the reading and loading of the software code are performed in response to determining that the software code stored at the third location in the common memory is not already stored in the second processor's local memory. 28. A computer program product stored on a computer memory, comprising computer program code that, when executed by an information handling system, causes the information handling system to perform actions comprising: loading data, by a first processor, to a first location in a common memory, wherein the common memory is shared by a plurality of heterogeneous processors in the information handling system;writing an instruction block, by the first processor, to a second location in the common memory, the instruction block identifying the first location and a third location in the common memory, the third location corresponding to software code that is configured to process the data;writing, by the first processor, the second location to a mailbox corresponding to a second processor from the plurality of heterogeneous processors in the information handling system;retrieving the instruction block, by the second processor, from the common memory in response to the first processor writing the second location to the mailbox;storing the data, by the second processor, in a local memory corresponding to the second processor in response to retrieving the instruction block;loading the software code, by the second processor, from the third location in the common memory to the second processor's local memory; andprocessing the data by the second processor using the software code loaded in the second processor's local memory. 29. The computer program product as described in claim 28 wherein the information handling system performs further actions comprising: writing, from a software program executing on the first processor, the data into an input buffer stored in the common memory, wherein the means for storing further includes means for sending the data from the input buffer into the second processor's local memory. 30. The computer program product as described in claim 29 wherein the sending the data into the second processor's local memory and the means for loading the software code are both performed using DMA operations. 31. The computer program product as described in claim 30 wherein the DMA operations are performed using one of a plurality of DMA controllers, one of which being assigned to the first processor and a second of which being assigned to the second processor. 32. The computer program product as described in claim 28 wherein the information handling system performs further actions comprising: generating result data, stored in the second processor's local memory, in response to the processing. 33. The computer program product as described in claim 32 wherein the information handling system performs further actions comprising: writing the result data to an output buffer stored in the common memory. 34. The computer program product as described in claim 32 wherein the information handling system performs further actions comprising: writing the result data to an input buffer located in another device. 35. The computer program product as described in claim 34 wherein the information handling system performs further actions comprising: signaling, from the second processor, a third processor from the plurality of heterogeneous processors, wherein the third processor includes a different local memory;storing the result data in the third processor's different local memory; andprocessing the result data by the third processor using other software code stored in the third processor's different local memory. 36. The computer program product as described in claim 32 wherein the information handling system performs further actions comprising: writing the result data to a physical device. 37. The computer program product as described in claim 28 wherein the software code stored in the second processor's local memory includes a plurality of code routines, the information handling system performing further actions comprising: identifying one of the code routines based upon the request; andexecuting the identified code routine. 38. The computer program product as described in claim 28 wherein the information handling system performs further actions comprising: initializing a task queue for one or more device functions to be performed by one or more of the plurality of heterogeneous processors, wherein the information handling system performs further actions comprising:writing the request to the task queue;determining, by the second processor, that the request is in the task queue; andreading the request from the task queue in response to the determination. 39. The computer program product as described in claim 28 wherein the information handling system performs further actions comprising: reading, by the second processor, the second location from the second processor's mailbox;reading, by the second processor, the first and third locations from the instruction block stored at the second location; andreading, by the second processor, the data from the first location in the common memory prior to storing the data in the second processor's local memory. 40. The computer program product as described in claim 28 wherein the information handling system performs further actions comprising: reading, by the second processor, the software code stored at the third location in the common memory. 41. The computer program product as described in claim 40 wherein the reading and the software code are performed in response to determining that the software code stored at the third location in the common memory is not already stored in the second processor's local memory. 42. A computer-implemented method for using a processor as a virtual device, said method comprising: loading data, by a first processor, to a first location in a common memory, wherein the common memory is shared by a plurality of heterogeneous processors in a computer system;writing an instruction block, by the first processor, to a second location in the common memory, the instruction block identifying the first location and a third location in the common memory, the third location corresponding to software code that is configured to process the data;writing, by the first processor, the second location to a mailbox corresponding to a second processor from a plurality of heterogeneous processors in a computer system;retrieving the instruction block, by the second processor, from the common memory in response to the first processor writing the second location to the mailbox;storing the data, by the second processor, in a local memory corresponding to the second processor in response to retrieving the instruction block;loading the software code, by the second processor, from the third location in the common memory to the second processor's local memory;processing the data by the second processor using the software code loaded in the second processor's local memory;generating result data by the second processor in response to the processing;writing the result data to an input buffer located in another device;signaling, from the second processor, a third processor from the plurality of heterogeneous processors, wherein the third processor includes a different local memory;storing the result data in the third processor's different local memory; andprocessing the result data by the third processor using different software code stored in the third processor's different local memory. 43. An information handling system comprising: a plurality of heterogeneous processors;a common memory shared by the plurality of heterogeneous processors;a first processor selected from the plurality of heterogeneous processors that sends a request to a second processor, the second processor also being selected from the plurality of heterogeneous processors;a local memory corresponding to the second processor;a DMA controller associated with the second processor, the DMA controller configured to transfer data between the common memory and the second processor's local memory; anda virtual device tool including software effective to: load data, by the first processor, to a first location in the common memory;write an instruction block, by the first processor, to a second location in the common memory, the instruction block identifying the first location and a third location in the common memory, the third location corresponding to software code that is configured to process the data;write, by the first processor, the second location to a mailbox corresponding to the second processor;retrieve the instruction block, by the second processor, from the common memory in response to the first processor writing the second location to the mailbox;store the data, by the second processor, in the local memory corresponding to the second processor in response to retrieving the instruction block;load the software code, by the second processor, from the third location in the common memory to the second processor's local memory;process the data by the second processor using the software code loaded in the second processor's local memory;generate result data by the second processor in response to the processing;write the result data to an input buffer located in another device;signal, from the second processor, a third processor from the plurality of heterogeneous processors, wherein the third processor includes a different local memory;store the result data in the third processor's different local memory; andprocess the result data by the third processor using different software code stored in the third processor's different local memory.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (97)
Andrew J. Fish ; William J. Clem, Arrangements having firmware support for different processor types.
Burke, Miles D.; Solar, Jr., Richard J., Building business objects and business software applications using dynamic object definitions of ingrediential objects.
Farrell Joel A. (Endicott NY) Record Stephen E. (Ridgefield CT) Wade Brian K. (Apalachin NY), Controlled scheduling of program threads in a multitasking operating system.
Getzinger Thomas W. (La Habra CA) Habereder Hans L. (Anaheim CA) Harrison R. Loyd (Fullerton CA) Hopp Donald M. (Fullerton CA) Mitchell David L. (Fullerton CA) Pian Chao-Kuang (Anaheim CA) Propster J, Data flow signal processor method and apparatus.
Correnti Joseph A. (Boca Raton FL) Pipitone Ralph M. (Boynton Beach FL) Thomas Michael W. (Bellevue WA), Data processing system and method having selectable scheduler.
Fischer,Claudius; Stephan,Thorsten; Schmidt,Markus; Hertweck,Jochen; M?ller,Franz, Device for running offline applications and synchronizing with a central computer system.
Hammond Steven W. (Schenectady NY), Finite element analysis method using multiprocessor for matrix manipulations with special handling of diagonal elements.
James Roxby,Philip B.; Ross,Charles A.; Schumacher,Paul R., Method and apparatus for processing data stored in a memory shared among a plurality of processors.
Matena,Vladimir; Sharma,Rahul; Mortazavi,Masood; Krishnan,Sanjeev, Method and apparatus for providing application specific strategies to a JAVA platform including load balancing policies.
King Adrian S. (Albuquerque NM), Method and apparatus for solving dense systems of linear equations with an iterative method that employs partial multipl.
Spix George A. ; Wengelski Diane M. ; Hawkinson Stuart W. ; Johnson Mark D. ; Burke Jeremiah D. ; Thompson Keith J. ; Gaertner Gregory G. ; Brussino Giacomo G. ; Hessel Richard E. ; Barkai David M. ;, Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes.
Timothy Proch ; Nick Horgan, Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses.
Miller,Matthew; Walker,Robert L., Method and system for managing distribution of computer-executable program threads between central processing units in a multi-central processing unit computer system.
Steinberg, Louis A.; Wetstone, Evan R.; Belousov, Arkadiy; Deuel, John, Method and system for reducing false alarms in network fault management systems.
Novaes,Marcos N.; Laib,Gregory D.; Goering,Ronald T.; Lucash,Jeffrey S.; Sohos,George, Method, system and program products for ordering lists of service addresses to provide load balancing of a clustered environment.
Hoffman Roy L. (Pine Island MN) Houdek Merle E. (Rochester MN) Loen Larry W. (Rochester MN) Soltis Frank G. (Rochester MN), Multi-processor task dispatching apparatus.
Reimer, Jay B.; Nguyen, Tai H.; Luo, Yi; Hopkins, Harland Glenn; Bui, Dan K.; McGonagle, Kevin A., Multicore DSP device having shared program memory with conditional write protection.
Spix George A. (Eau Claire WI) Wengelski Diane M. (Eau Claire WI) Hawkinson Stuart W. (Eau Claire WI) Johnson Mark D. (Eau Claire WI) Burke Jeremiah D. (Eau Claire WI) Thompson Keith J. (Eau Claire W, System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel executi.
Yamazaki Shigemi,JPX ; Mukai Kazunari,JPX ; Tajima Yoshihiro,JPX ; Kohge Kiyoshi,JPX ; Komiyama Takashi,JPX, System and method for executing job between different operating systems.
Demsey,Seth M.; Smith,Brian J.; Corbin,Scott M.; Smith,Michael D.; Zintel,W. Michael, System and method for jointly managing dynamically generated code and data.
Faustini, Antony Azio, System, method and article of manufacture for creating an object oriented component having multiple bidirectional ports for use in association with a java application or applet.
Rusterholz John T. (Roseville MN) Homan Charles J. (St. Paul MN) Brown Lowell E. (Anoka MN) Bennett Donald B. (Burnsville MN) Malnati Robert J. (St. Paul MN) Hamstra James R. (Plymouth MN), Tightly coupled scientific processing system.
Guttag Karl M. (Sugar Land TX) Read Christopher J. (Houston TX) Poland Sydney W. (Katy TX) Gove Robert J. (Plano TX) Golston Jeremiah E. (Sugar Land TX), Transfer processor with transparency.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.