[특허]Adhesive/spacer island structure for stacking over wire bonded die

[미국특허] Adhesive/spacer island structure for stacking over wire bonded die 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/48 H01L-023/52
출원번호	US-0134845 (2005-05-20)
등록번호	US-8552551 (2013-10-08)
발명자 / 주소	Lee, Sang Ho Ju, Jong Wook Kwon, Hyeog Chan Karnezos, Marcos
출원인 / 주소	CHIPPAC, Inc.
대리인 / 주소	Ishimaru & Associates LLP
인용정보	피인용 횟수 : 2 인용 특허 : 135

초록 ▼

Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate or so that the die attach side of the upper package faces away from the lower die or lower package substrate.

대표청구항 ▼

1. A multiple-die semiconductor chip package comprising: a substrate;a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface;wires bonded to and extending from the bond pads outwardly past the periphery to the substrate;a second die with an electrically non-conductive second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer entirely covering the second surface;a plurality of spaced-apart adhesive/spacer islands within the die bonding region securing the first and second die to one another at a chosen separation to create a multiple-die assembly, the adhesive/spacer islands including deformable spacer elements having a generally ellipsoidal shape and occupying a first percentage of the die bonding region;the adhesive/spacer islands comprising at least one spacer element within an adhesive; anda material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region. 2. The package according to claim 1 wherein the first percentage is between about 20-50 percent. 3. The package according to claim 1 wherein the first percentage is at most about 50%. 4. The package according to claim 1 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100 percent thereby effectively eliminating voids within the die bonding region. 5. The package according to claim 1 wherein: the adhesive comprises epoxy; andthe encapsulating material comprises a filled epoxy. 6. The package according to claim 1 wherein the adhesive and the encapsulating material create an adhesive/encapsulating material boundary within the die bonding region. 7. A stacked semiconductor assembly comprising: a first semiconductor device having a first surface bounded by a periphery and having bond pads at the first surface;wires bonded to and extending from the bond pads outwardly past the periphery, the wires extending to a maximum height h above the first device;a package, comprising a package die mounted to and electrically interconnected with a package substrate, the package having an electrically non-conductive second surface positioned opposite the first surface, the package comprising a dielectric layer entirely covering the second surface of the package;the first device and the package defining a first region therebetween;an adhesive/spacer structure within the first region, the adhesive/spacer structure contacting the first and second surfaces and adhering the first device and the package to one another at a chosen separation, the adhesive/spacer structure comprising deformable spacer elements within an adhesive, and a material encapsulating the stacked assembly, the encapsulating material occupying the first region. 8. The stacked semiconductor assembly of claim 7 wherein the package is oriented so that the die attach side of the upper package substrate faces the first device. 9. The stacked semiconductor assembly of claim 7 wherein the package is oriented so that side of the upper package substrate opposite the die attach side faces the first die. 10. Stacked semiconductor packages comprising the assembly of claim 7. 11. A multiple-die semiconductor chip package comprising: a substrate;a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface;wires bonded to and extending from the bond pads outwardly past the periphery to the substrate;a second die with an electrically non-conductive second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer entirely covering the second surface;adhesive/spacer structure within the die bonding region securing the first and second surfaces to one another at a chosen separation to create a multiple-die assembly;the adhesive/spacer structure comprising deformable spacer elements within an adhesive;the adhesive/spacer structure occupying a first percentage of the die bonding region, the first percentage being at most about 50%; anda material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region. 12. The package according to claim 11 wherein the first percentage is about 20-50%. 13. The package according to claim 11 wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.

이 특허에 인용된 특허 (135) 인용/피인용 타임라인 분석

He, Xiping; Dominic, Christopher J., Adhesive wafers for die attach application.
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Korleski Joseph E., Adhisive-filler polymer film composite.
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Syed Sajid Ahmad, Apparatus for applying viscous materials to a lead frame.
상세보기
Derderian, James M., Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods.
상세보기
Makoto Terui JP, BGA package and method for fabricating the same.
상세보기
Fee, Setho Sing; Chye, Lim Thiam; Heppler, Steven W.; Yin, Leng Nam; Tan, Keith; Guay, Patrick; Tian, Edmund Lua Koon; Eng, Yap Kah; Seng, Eric Tan Swee, Ball grid array interposer, packages and methods.
상세보기
Kaul Sunil (Fremont CA) Laird Douglas A. (Los Gatos CA), Ball grid array packages for high speed applications.
상세보기
Koopmans, Michel, Bumping technology in stacked die configurations.
상세보기
Culnane Thomas Moran ; Gaynes Michael Anthony ; Seto Ping Kwong ; Shaukatullah Hussain, Chip carrier modules with heat sinks attached by flexible-epoxy.
상세보기
Akram, Salman, Chip package with grease heat sink.
상세보기
Shyue Fong Quek MY; Ying Keung Leung SG; Sang Yee Loong SG; Ting Cheong Ang SG, Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection.
상세보기
Heim Craig G. ; Hooker Wade Leslie ; Trivedi Ajit Kumar, Cooling structure for electronic components.
상세보기
Wu, Chi-Chuan; Huang, Chien-Ping, Crack-preventive semiconductor package.
상세보기
Barrow Michael, Custom corner attach heat sink design for a plastic ball grid array integrated circuit package.
상세보기
Shores A. Andrew (Venice CA), Die attach adhesive film, application method and devices incorporating the same.
상세보기
Watson, Michael John, Die attach adhesives for semiconductor applications utilizing a polymeric base material with inorganic insulator particles of various sizes.
상세보기
Choi, Ill Heung, Duel die package.
상세보기
Goller, Bernd; Ofner, Gerald; Thumbs, Josef; Worner, Holger; Hagen, Robert-Christian; Stumpfl, Christian; Wein, Stefan, Electronic component with at least two stacked semiconductor chips and method for fabricating the electronic component.
상세보기
Combs, Edward G.; Sheppard, Robert P.; Pun, Tai Wai; Ng, Hau Wan; Fan, Chun Ho; McLellen, Neil Robert, Enhanced thermal dissipation integrated circuit package.
상세보기
Moden Walter L., Flip chip adaptor package for bare die.
상세보기
Moden, Walter L., Flip chip adaptor package for bare die.
상세보기
Moden, Walter L., Flip chip adaptor package for bare die.
상세보기
Song, Young-Jae; Kwon, Young-Shin; Youm, Kun-Dae; Kim, Young-Soo, Higher-density memory card.
상세보기
Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.
상세보기
Farnworth Warren M. (Boise ID), Inset die lead frame configuration lead frame for a semiconductor device having means for improved busing and die-lead f.
상세보기
Farquhar, Donald Seton; Jimarez, Lisa Jeanine; Klodowski, Michael Joseph; Zimmerman, Jeffrey Alan, Integrated circuit chip carrier assembly.
상세보기
Hisashi Takeda JP, Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board.
상세보기
Song Young-Jae,KRX ; Seo Jeong-Woo,KRX ; Kim Kyung-Seop,KRX, Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and me.
상세보기
Maeda, Takehiko; Tsukano, Jun, Light thin stacked package semiconductor device and process for fabrication thereof.
상세보기
Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.
상세보기
Lee Shaw Wei (San Jose CA), Maximized substrate design for grid array based assemblies.
상세보기
Nguyen Luu ; Prabhu Ashok ; Kelkar Nikhil ; Takiar Hem P., Method and apparatus for forming a plastic chip on chip package module.
상세보기
Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.
상세보기
Koopmans, Michel, Method of fabricating stacked die configurations utilizing redistribution bond pads.
상세보기
Glenn, Thomas P.; Smith, Lee J.; Zoba, David A.; Ramakrishna, Kambhampati; DiCaprio, Vincent, Method of making a semiconductor package including stacked semiconductor dies.
상세보기
Tomihara, Seiichi, Method of manufacturing a semiconductor device having flexible wiring substrate.
상세보기
Kakimoto Noriko,JPX ; Suematsu Eiji,JPX, Millimeter wave semiconductor device.
상세보기
Pu, Han-Ping; Huang, Chih-Ming; Huang, Chien-Ping, Module device of stacked semiconductor packages and method for fabricating the same.
상세보기
Michael B. Ball, Multi-chip device utilizing a flip chip and wire bond assembly.
상세보기
Jao Jui-Meng,TWX ; Ko Eric,TWX ; Liu Vicky,TWX, Multi-chip integrated circuit package structure for central pad chip.
상세보기
Ming-Hsun Lee TW; Chin-Te Chen TW, Multi-chip module.
상세보기
Vaiyapuri Venkateshwaran,SGX ; Yang Jicheng,SGX, Multi-chip module with stacked dice.
상세보기
Liu,Cheng Cheng, Multi-chip package combining wire-bonding and flip-chip configuration.
상세보기
Kao-Yu Hsu TW; Su Tao TW, Multichip module.
상세보기
Liu, Chung-Lun; Chang, Chin-Huang, Multichip module.
상세보기
Fogal Rich (Boise ID) Ball Michael B. (Boise ID), Multichip module having a stacked chip arrangement.
상세보기
Lin Chun Hung,TWX, Multichip module having stacked chip arrangement.
상세보기
Michii, Kazunari; Akiyama, Tatsuhiko, Multiple chip package semiconductor device.
상세보기
Salman Akram, Multiple die stack apparatus employing T-shaped interposer elements.
상세보기
Lo, Randy H. Y.; Huang, Chien-Ping; Wu, Chi-Chuan, Multiple stacked-chip packaging structure.
상세보기
Chaudhuri, Arun K.; Workman, Derek B.; Walsh, Matthew R., No-flow underfill material and underfill method for flip chip devices.
상세보기
Jeansonne Jeff K., Opposed ball grid array mounting.
상세보기
Shim, Il Kwon; Chow, Seng Guan; Balanon, Gerry, PBGA substrate for anchoring heat sink.
상세보기
Junichi Asada JP, Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same.
상세보기
Chen, Jian-Cheng; Hsiao, Wei-Min, Package of a chip with beveled edges.
상세보기
Chye, Lim Thiam; Fee, Setho Sing; Seng, Eric Tan Swee, Packaged microelectronic component assemblies.
상세보기
Ziegler James F., Process for fabricating single crystal resonant devices that are compatible with integrated circuit processing.
상세보기
Hsu, Chi-Hsing, Quad flat no-lead chip carrier.
상세보기
Uchida, Yasufumi; Saeki, Yoshihiro, Rearrangement sheet, semiconductor device and method of manufacturing thereof.
상세보기
Belgacem Haba ; Donald V. Perino ; Sayeh Khalili, Redistributed bond pads in stacked integrated circuit die package.
상세보기
Ichinose, Michihiko; Takizawa, Tomoko; Honda, Hirokazu; Kata, Keiichirou, Resin-encapsulated semiconductor device.
상세보기
Kondo, Takashi; Bando, Koji; Shibata, Jun; Narutaki, Kazuko, Resin-sealed chip stack type semiconductor device.
상세보기
Benenati Joseph A. ; Bertin Claude L. ; Chen William T. ; Dinan Thomas E. ; Ellis Wayne F. ; Howell Wayne J. ; Knickerbocker John U. ; Pierson Mark V. ; Tonti William R. ; Zalesinski Jerzy M., Rolling ball connector.
상세보기
Hideki Ishii JP; Kazunari Michii JP; Jun Shibata JP; Moriyoshi Nakashima JP, Semiconductor device.
상세보기
Ichikawa, Sunji, Semiconductor device.
상세보기
Ozawa Kaname,JPX ; Okuda Hayato,JPX ; Hiraoka Tetsuya,JPX ; Sato Mitsutaka,JPX ; Akashi Yuji,JPX ; Okada Akira,JPX ; Harayama Masahiko,JPX, Semiconductor device.
상세보기
Tadashi Komiyama JP, Semiconductor device.
상세보기
Terui, Makoto, Semiconductor device.
상세보기
Kurita, Yoichiro; Shironouchi, Toshiaki; Tetsuka, Takashi, Semiconductor device and method for manufacturing the same.
상세보기
Ohuchi Shinji,JPX ; Yamada Shigeru,JPX ; Shiraishi Yasushi,JPX, Semiconductor device and method for manufacturing the same.
상세보기
Nakayama, Hirohisa; Taniguchi, Jun; Abe, Takashi; Nakayama, Toshinori, Semiconductor device and method of fabricating the same, circuit board, and electronic equipment.
상세보기
Emoto, Yoshiaki, Semiconductor device and method of making the same, circuit board and electronic equipment.
상세보기
Ichinose, Michihiko, Semiconductor device and packaging method thereof.
상세보기
Jiang, Tongbi; Fee, Setho Sing; Yean, Tay Wuu; Chye, Lim Thiam, Semiconductor device assemblies and packages including multiple semiconductor devices and methods.
상세보기
Fumihiko Taniguchi JP; Akira Takashima JP, Semiconductor device having an interconnecting post formed on an interposer within a sealing resin.
상세보기
Uchida, Yasufumi, Semiconductor device having multi-chip package.
상세보기
Fogal Rich (Boise ID) King Jerrold L. (Boise ID) Moden Walter L. (Boise ID), Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic cov.
상세보기
Tamaki Kazuo,JPX ; Saza Yasuyuki,JPX ; Dotta Yoshihisa,JPX, Semiconductor device using a chip scale package.
상세보기
Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.
상세보기
Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package.
상세보기
Karnezos, Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages.
상세보기
Karnezos, Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield.
상세보기
Karnezos, Marcos, Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages.
상세보기
Karnezos,Marcos, Semiconductor multipackage module including processor and memory package assemblies.
상세보기
Liao, Chih-Chin; Pu, Han-PIng; Huang, Chien-Ping, Semiconductor package.
상세보기
Tzu Chung-Hsing,TWX, Semiconductor package having multi-dies.
상세보기
Thomas P. Glenn ; Lee J. Smith ; David A. Zoba ; Kambhampati Ramakrishna ; Vincent DiCaprio, Semiconductor package including stacked semiconductor dies and bond wires.
상세보기
Huang, Chien-Ping, Semiconductor package with flash-proof device.
상세보기
Akram, Salman; Brooks, Jerry M., Semiconductor package with stacked substrates and multiple semiconductor dice.
상세보기
Karnezos,Marcos, Semiconductor stacked multi-package module having inverted second package.
상세보기
Karnezos, Marcos, Semiconductor stacked multi-package module having inverted second package and electrically shielded first package.
상세보기
Lin Paul T. (Austin TX), Shielded liquid encapsulated semiconductor device and method for making the same.
상세보기
Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock resistant semiconductor device and method for producing same.
상세보기
De Givry Jacques (Les Loges En Josas FRX), Solid state memory modules and memory devices including such modules.
상세보기
Yang,Chaur Chin; Wang,Hsueh Te, Stack type flip-chip package.
상세보기
Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.
상세보기
Tao Su,TWX ; Lo Kuang-Lin,TWX ; Chou Kuang-Chun,TWX ; Chen Shih-Chih,TWX, Stacked chip assembly utilizing a lead frame.
상세보기
McMahon, John F., Stacked chip packaging.
상세보기
Levardo, Melvin N.; Gonzales, Marcelo S., Stacked dice standoffs.
상세보기
Lo, Wai Yew; Aripin, Azhar Bin; Tiu, Kong Bee, Stacked die semiconductor device.
상세보기
Akram Salman, Stacked leads-over chip multi-chip module.
상세보기
Mess, Leonard E.; Brooks, Jerry M.; Corisis, David J., Stacked mass storage flash memory package.
상세보기
Corisis, David J., Stacked microelectronic dies and methods for stacking microelectronic dies.
상세보기
Degani, Yinon; Dudderar, Thomas Dixon; Sun, Liguo; Zhao, Meng, Stacked module package.
상세보기
Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.
상세보기
Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Nishimura, Takao, Stacked semiconductor device and method of producing the same.
상세보기
Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Uno, Tadashi; Nishimura, Takao; Ando, Fumihiko; Onodera, Hiroshi; Okuda, Hayato, Stacked semiconductor device and method of producing the same.
상세보기
St. Amand, Roger D.; Perelman, Vladimir, Stacked semiconductor die assembly having at least one support.
상세보기
Baek, Joong-hyun; Lee, Jin-yang; Im, Yun-hyeok; Lee, Tae-koo, Stacked semiconductor module and method of manufacturing the same.
상세보기
Pedron, Jr., Serafin P., Stacked semiconductor package and method of manufacturing the same.
상세보기
Jichen Wu TW; Meng Ru Tsai TW; Nai Hua Yeh TW; Chen Pin Peng TW, Stacked structure of semiconductor means and method for manufacturing the same.
상세보기
St. Amand,Roger D.; Kim,InTae; Perelman,Vladimir, Stacked-die extension support structure and method thereof.
상세보기
Pu, Han-Ping; Lo, Randy H. Y.; Her, Tzong-Dar; Huang, Chien-Ping; Hsiao, Cheng-Shiu; Wu, Chi-Chuan, Stacked-die package structure.
상세보기
Corbett Tim J. ; Moden Walter L., Structure for attaching a semiconductor wafer section to a support.
상세보기
Her, Tzong-Dar; Lo, Randy H. Y.; Huang, Chien-Ping, Structure of a multi chip module having stacked chips.
상세보기
Wen Chuan Chen TW; Kuo Feng Peng TW; Jichen Wu TW; Chia Jung Chang TW, Structure of stacked integrated circuits.
상세보기
Hoffman, Paul Robert; Zoba, David Albert, Structures for improving heat dissipation in stacked semiconductor packages.
상세보기
Halahan, Patrick B., Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity.
상세보기
Hur, Hyeong Ryeol; Bathan, Henry D.; Camacho, Zigmund R., System for semiconductor package with stacked dies.
상세보기
Nguyen, Luu Thanh; Pham, Ken; Deane, Peter; Mazotti, William Paul; Roberts, Bruce Carlton; Liu, Jia, Techniques for joining an opto-electronic module to a semiconductor package.
상세보기
Nguyen,Luu Thanh; Pham,Ken; Deane,Peter; Mazotti,William Paul; Roberts,Bruce Carlton; Liu,Jia, Techniques for joining an opto-electronic module to a semiconductor package.
상세보기
Rostoker Michael D. (Boulder Creek CA), Techniques for providing high I/O count connections to semiconductor dies.
상세보기
Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
상세보기
Chen, Eing-Chieh; Lai, Cheng-Yuan; Tien, Tzu-Yi, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
상세보기
Eing-Chieh Chen TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
상세보기
Hawke Robert E.,CAX ; Patel Atin J.,CAX ; Binapal Sukhminder S.,CAX ; Divita Charles,CAX ; McNeil Lynn,CAX ; Fletcher Thomas G.,CAX, Three dimensional packaging configuration for multi-chip module assembly.
상세보기
Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
상세보기
Massit Claude (Ismier FRX) Nicolas Grard (Voreppe FRX), Three-dimensional multichip module.
상세보기
Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.
상세보기

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Adhesive/spacer island structure for stacking over wire bonded die 원문보기

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[미국특허] Adhesive/spacer island structure for stacking over wire bonded die 원문보기

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대표청구항 ▼

연구과제 타임라인

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이 특허에 인용된 특허 (135) 인용/피인용 타임라인 분석

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