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A display control apparatus includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of image data. The comparison control unit includes a region control unit which selects a region of the image data based on comparison region information for specifying an

A display control apparatus includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of image data. The comparison control unit includes a region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value. Error detection by the cyclic redundancy check is performed only on the target region of the cyclic redundancy check in the arbitrary region, which facilitates the cyclic redundancy check.

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1. A display control apparatus comprising: a display output control unit for performing display control of image data on a display unit, anda CPU which can control operation of the display output control unit,whereinthe display output control unit includes a comparison control unit which performs a

1. A display control apparatus comprising: a display output control unit for performing display control of image data on a display unit, anda CPU which can control operation of the display output control unit,whereinthe display output control unit includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of the image data displayed on the display unit, andthe comparison control unit includes a region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit which performs arithmetic processing for a cyclic redundancy check over a region selected by the region control unit, and a comparison circuit which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with an expected value. 2. The display control apparatus according to claim 1, wherein the display output control unit further includes a plurality of plane control units for receiving different image data respectively, and an overlay control unit which forms image data to be displayed by overlaying the image data received by the plane control unit, and wherein the comparison control unit further includes a selector which can supply output image information of the plane control unit or output image information of the overlay control unit selectively to the arithmetic processing unit. 3. The display control apparatus according to claim 2, wherein a plurality of the comparison control units is provided, the comparison control units performing, in parallel, the cyclic redundancy check over an arbitrary region of the image data respectively displayed on the display unit. 4. The display control apparatus according to claim 2, wherein the comparison control unit displays an error message on the display unit based on the result of the comparison by the comparison circuit, and turns on a warning light provided near the display unit. 5. The display control apparatus according to claim 2, further comprising: a selection information register which holds control information of the selector;a selection update information register which holds update information of the control information in the selection information register;a comparison region information register which holds the comparison region information;a comparison region update information register which holds update information of the comparison region information in the comparison region information register;an expected value information register which holds an expected value of the results of the arithmetic processing by the arithmetic processing unit; andan expected value update information register which holds update information of the expected value in the expected value information register,wherein the information held in the selection information register is updated by the information held in the selection update information register in synchronization with a vertical synchronizing signal of the display unit,wherein the information held in the comparison region information register is updated by the information held in the comparison region update information register in synchronization with the vertical synchronizing signal of the display unit, andwherein the information held in the expected value information register is updated by the information held in the expected value update information register in synchronization with the vertical synchronizing signal of the display unit. 6. The display control apparatus according to claim 2, wherein the comparison control unit includes an interrupt control circuit which forms an interrupt control signal for requesting an interrupt to the CPU based on the result of the comparison by the comparison circuit,wherein the interrupt control circuit includes a counter for counting the number of erroneous frames based on the result of the comparison by the comparison circuit, and a comparator for comparing the value counted by the counter with a predetermined threshold, andwherein the interrupt control signal is asserted, based on the result of the comparison by the comparator. 7. The display control apparatus according to claim 2, wherein the comparison control unit includes an interrupt control circuit which forms an interrupt control signal for requesting an interrupt to the CPU based on the result of the comparison by the comparison circuit, andwherein the interrupt control circuit includes a plurality of counters for counting the number of erroneous frames based on the result of the comparison by the comparison circuit, a counter selection control unit for selecting the counters, and a comparator for comparing the value counted by the counter selected by the counter selection control unit with a predetermined threshold, andwherein the interrupt control signal is asserted, based on the result of the comparison by the comparator. 8. The display control apparatus according to claim 2, further comprising a first buffer for externally outputting the image data output from the display output control unit; anda second buffer for receiving the image data externally output via the first buffer into the display control apparatus again,wherein the display output control unit includes a selector for transmitting the output of the first buffer and the output of the second buffer selectively to the comparison control unit. 9. A display control apparatus comprising: a display output control unit for performing display control of image data on a display unit;a CPU which can control the operation of the display output control unit;a first buffer for externally outputting the image data output from the display output control unit; anda second buffer for receiving the image data externally output via the first buffer into the display control apparatus again,wherein the display output control unit includes a loop-back comparison control unit which performs error detection over an arbitrary region of the image displayed on the display unit, and a selector which transmits the output of the first buffer and the output of the second buffer selectively to the loop-back comparison control unit, andwherein the loop-back comparison control unit includes a region control unit which selects a region of the image data based on region update information for specifying an arbitrary region of the image displayed on the display unit as a region to be checked, and a bit comparison processing unit which performs error detection by comparing the image data input to the first buffer with the image data transmitted via the selector in a bit-by-bit manner over the region selected by the region control unit. 10. The display control apparatus according to claim 9, wherein the bit comparison processing unit includes a delay circuit for delaying the image data input to the first buffer, and it is determined that no error exists if the output data of the delay circuit matches the image data transmitted via the selector. 11. A display control device comprising: a display output control unit for performing display control of image data on a display unit;a CPU which can control the operation of the display output control unit;a first buffer for externally outputting the image data output from the display output control unit; anda second buffer for receiving the image data externally output via the first buffer into the display control apparatus again,wherein the display output control unit includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of the image displayed on the display unit, and a loop-back comparison control unit which performs error detection over an arbitrary region of the image data displayed on the display unit,wherein the comparison control unit includes a first region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image data displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit which performs arithmetic processing for the cyclic redundancy check over a region selected by the first region control unit, and a comparison circuit which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value, andwherein the loop-back comparison control unit includes a second region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a region to be checked, a selector for transmitting the output of the first buffer and the output of the second buffer selectively to the loop-back comparison control unit, and a bit comparison processing unit which performs error detection by comparing the image data input to the first buffer with the image data transmitted via the selector in a bit-by-bit manner over the region selected by the second region control unit. 12. A display control apparatus comprising: a region control unit which selects a cyclic redundancy check target region based on comparison region information for specifying an arbitrary region of the first image data,an arithmetic processing unit which performs a predetermine arithmetic processing for a cyclic redundancy check over the cyclic redundancy check target region,a comparison circuit which performs error detection by comparing the result of the predetermined arithmetic processing with a predetermined value, andwherein the display control apparatus outputs second image data based on first image data to a display unit. 13. A display control apparatus according to claim 12, further comprising: a CPU which can control the operation of the outputting of the second image data,an interrupt control circuit which forms an interrupt control signal for requesting an interrupt to the CPU based on the result of the comparison by the comparison circuit,wherein the interrupt control circuit includes a counter for counting the number of erroneous frames based on the result of the comparison by the comparison circuit, and a comparator for comparing the value counted by the counter with a predetermined threshold, andwherein the interrupt control signal is asserted, based on the result of the comparison by the comparator. 14. A display control apparatus according to claim 12, further comprising: a CPU which can control the operation of the outputting of the second image data,an interrupt control circuit which forms an interrupt control signal for requesting an interrupt to the CPU based on the result of the comparison by the comparison circuit, andwherein the interrupt control circuit includes a plurality of counters for counting the number of erroneous frames based on the result of the comparison by the comparison circuit, a counter selection control unit for selecting the counters, and a comparator for comparing the value counted by the counter selected by the counter selection control unit with a predetermined threshold, andwherein the interrupt control signal is asserted, based on the result of the comparison by the comparator. 15. A display control apparatus according to claim 12, further comprising: a plurality of plane control units for receiving different image data respectively, and an overlay control unit which forms image data to be displayed by overlaying the image data received by the plane control unit, anda selector which can supply output image information of the plane control unit or output image information of the overlay control unit selectively to the arithmetic processing unit. 16. A display control apparatus according to claim 15, further comprising: a selection information register which holds control information of the selector;a selection update information register which holds update information of the control information in the selection information register;a comparison region information register which holds the comparison region information;a comparison region update information register which holds update information of the comparison region information in the comparison region information register;an expected value information register which holds an expected value of the results of the arithmetic processing by the arithmetic processing unit; andan expected value update information register which holds update information of the expected value in the expected value information register,wherein the information held in the selection information register is updated by the information held in the selection update information register in synchronization with a vertical synchronizing signal of the display unit,wherein the information held in the comparison region information register is updated by the information held in the comparison region update information register in synchronization with the vertical synchronizing signal of the display unit, andwherein the information held in the expected value information register is updated by the information held in the expected value update information register in synchronization with the vertical synchronizing signal of the display unit. 17. A display control apparatus according to claim 15, wherein an error message is displayed on the display unit based on the result of the comparison by the comparison circuit.