Lithography for printing constant line width features
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/302
H01L-029/00
C23F-001/00
출원번호
US-0047037
(2011-03-14)
등록번호
US-8592946
(2013-11-26)
발명자
/ 주소
Zhu, Huilong
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Scully, Scott, Murphy & Presser, P.C.
인용정보
피인용 횟수 :
0인용 특허 :
13
초록▼
An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation o
An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.
대표청구항▼
1. A semiconductor structure comprising: a stack located on a semiconductor substrate and comprising, from bottom to top, a gate dielectric layer, a gate conductor layer, a dielectric oxide layer, and a semiconductor layer, wherein said semiconductor layer contains a pair of crystallographic facets
1. A semiconductor structure comprising: a stack located on a semiconductor substrate and comprising, from bottom to top, a gate dielectric layer, a gate conductor layer, a dielectric oxide layer, and a semiconductor layer, wherein said semiconductor layer contains a pair of crystallographic facets joined by a ridge; andan undamaged masking material portion located directly on said ridge and having a vertical cross-sectional area of a rhombus consisting of four straight sides of equal length. 2. The semiconductor structure of claim 1, further comprising implantation damaged masking material portions containing Ge, B, Ga, In, As, P, Sb, or inert atoms and abutting one of said pair of crystallographic facets and said undamaged masking material portion, wherein said undamaged masking material portion does not contain Ge, B, Ga, In, As, P, Sb, or inert atoms. 3. The semiconductor structure of claim 2, wherein said semiconductor layer contains a horizontal surface vertically abutting one of said implantation-damaged masking material portions. 4. The semiconductor structure of claim 2, wherein said undamaged masking material portion and said implantation-damaged masking material portions differ in composition only by said Ge or said inert atoms. 5. The semiconductor structure of claim 2, wherein said inert atoms comprise at least one of Ne, Ar, Kr, Xe, and Rn. 6. The semiconductor structure of claim 1, further comprising at least one shallow trench isolation structure comprising a dielectric material and located in said semiconductor substrate. 7. The semiconductor structure of claim 1, wherein surface orientations of said crystallographic facets are one of {100} orientations, {110} orientations, {111} orientations, {211} orientations, {221} orientations, and {311} orientations. 8. The semiconductor structure of claim 1, wherein said rhombus has a sublithographic width. 9. The semiconductor structure of claim 1, wherein a corner of said rhombus coincides with a point on said ridge. 10. The semiconductor structure of claim 1, wherein said undamaged masking material portion comprises a dielectric material. 11. A semiconductor structure comprising: a stack located on a semiconductor substrate and comprising, from bottom to top, a gate dielectric layer, a gate conductor layer, a dielectric oxide layer, and a semiconductor layer, wherein said semiconductor layer contains a pair of crystallographic facets joined by a ridge;an undamaged masking material portion located directly on said ridge and having a vertical cross-sectional area of a rhombus; andimplantation damaged masking material portions containing Ge, B, Ga, In, As, P, Sb, or inert atoms and abutting one of said pair of crystallographic facets and said undamaged masking material portion, wherein said undamaged masking material portion does not contain Ge, B, Ga, In, As, P, Sb, or inert atoms, wherein said undamaged masking material portion and said implantation-damaged masking material portions differ in composition only by said Ge or said inert atoms. 12. The semiconductor structure of claim 11, wherein said semiconductor layer contains a horizontal surface vertically abutting one of said implantation-damaged masking material portions. 13. The semiconductor structure of claim 11, wherein said inert atoms comprise at least one of Ne, Ar, Kr, Xe, and Rn. 14. The semiconductor structure of claim 11, further comprising at least one shallow trench isolation structure comprising a dielectric material and located in said semiconductor substrate. 15. The semiconductor structure of claim 11, wherein surface orientations of said crystallographic facets are one of {100} orientations, {110} orientations, {111} orientations, {211} orientations, {221} orientations, and {311} orientations. 16. The semiconductor structure of claim 11, wherein said rhombus has a sublithographic width.
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이 특허에 인용된 특허 (13)
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