초록 ▼

A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive p

A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

대표청구항 ▼

1. A method of controlling electromagnetic waves in a device, the method comprising: providing a first conductive layer;providing a patch layer having conductive patches, the conductive patches connected by an inductive element;providing a conductive element disposed between the first layer and at l

1. A method of controlling electromagnetic waves in a device, the method comprising: providing a first conductive layer;providing a patch layer having conductive patches, the conductive patches connected by an inductive element;providing a conductive element disposed between the first layer and at least one of the conductive patches and electrically connected to one of the first layer or the at least one of the conductive patches; andproviding a capacitive element disposed to couple between the conductive element and at least one of the at least one of the conductive patches, or to the first layer,wherein the inductive element is a coupled transmission line and the first conductive layer has an opening defining a slot disposed so as to be aligned with a portion of the coupled transmission line. 2. The method of claim 1, wherein characteristics of one or more of the conductive patches, an inductance of the inductive element, a dielectric constant of a dielectric layer disposed between the first layer and the patch layer, or the capacitance of the capacitive element, are selected to control a stop band characteristic frequency. 3. The method of claim 1, further comprising spacing the first layer and the patch layer in substantially parallel planes. 4. The method of claim 1, further comprising selecting at least one of a distance between adjacent patches, a size of the patches, or a length, width, or spacing of the coupled transmission line so as to control a characteristic frequency of an electromagnetic stop band. 5. The method of claim 1, further comprising disposing the first layer and the conductive patches so as to comprise a power distribution network. 6. The method of claim 1, further comprising disposing the conductive patches in a one dimensional array to form a conductive path in a power distribution network. 7. The method of claim 1, further comprising disposing the conductive patches between a noise generating component of a circuit and a noise susceptible component of the circuit. 8. The method of claim 1, further comprising incorporating the first conductive layer, the conductive patches, and the conductive element in a printed circuit board. 9. The method of claim 1, incorporating the first conductive layer, the conductive patches and the conductive element a in a multi chip module. 10. The method of claim 1, further comprising incorporating the first conductive layer, the conductive patches and the conductive element in a semiconductor chip. 11. The method of claim 1, further comprising configuring the device as a stripline. 12. The method of claim 1, further comprising configuring the device as a microstripline.