초록 ▼

A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a fi

A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup. The second switch (196) is capable to connect the third bias voltage (164) and an inner drain-source connection (130) in the output stage of the first cascode current mirror (116) during startup.

대표청구항 ▼

1. A self-biased reference circuit device, said device comprising: a first cascode current mirror operable to generate first and second bias voltages in response to a first current and to generate a second current in response to the first and second bias voltages;a second cascode current mirror oper

1. A self-biased reference circuit device, said device comprising: a first cascode current mirror operable to generate first and second bias voltages in response to a first current and to generate a second current in response to the first and second bias voltages;a second cascode current mirror operable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages; anda startup circuit comprising a first switch in a first start-up branch and a second switch in a second start-up branch, wherein the first switch is operable to communicatively couple the first and fourth bias voltages during startup and wherein the second switch is operable to communicatively couple the third bias voltage and an inner drain-source connection in the output stage of the first cascode current mirror during startup, where, enabled by said first start-up branch, said second switch ensures current flow in said second start-up branch. 2. The device of claim 1 further comprising a resistor communicatively coupled between the first cascode current mirror and a voltage source. 3. The device of claim 1 wherein the first and second switches are transistors. 4. The device of claim 1 wherein the startup circuit further comprises a timing means operable to control the timing of the first and second switches. 5. The device of claim 4 wherein the timing means comprises a transistor and a capacitor. 6. The device of claim 1 wherein the first cascode current mirror comprises first, second, third, and fourth transistors, wherein the first and second transistors are cascode-stacked and diode-connected, wherein the third and fourth transistors are cascode-stacked, wherein the drain and gate of the first transistor are communicatively coupled to the gate of the third transistor and correspond to the first bias voltage, wherein the drain and gate of the second transistor are communicatively coupled to the gate of the fourth transistor and correspond to the second bias voltage. 7. The device of claim 6 further comprising a resistor communicatively coupled between the source of the third transistor and a voltage source. 8. The device of claim 1 wherein the second cascode current mirror comprises first, second, third, fourth, and fifth transistors, wherein the first and second transistors are cascode-stacked, wherein the third and fourth transistors are cascode-stacked, wherein the gates of the first and third transistors are communicatively coupled to the drain of the fourth transistor and correspond to the third bias voltage, wherein the fifth transistor is diode-connected, and wherein the drain and gate of the fifth transistor is communicatively coupled to the gates of the second and fourth transistors and correspond to the fourth bias voltage. 9. The device of claim 8 further comprising a resistor communicatively coupled between the source of the third transistor and a voltage source. 10. A self-biased reference circuit device, said device comprising: a first cascode current mirror operable to generate a first bias voltage in response to a first current, to generate a second bias voltage in response to a fourth current, and to generate a second current in response to the first and second bias voltages;a second cascode current mirror operable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages; anda startup circuit comprising a first switch in a first start-up branch and a second switch in a second start-up branch, wherein the first switch is operable to communicatively couple the first and fourth bias voltages during startup, wherein the second switch is operable to communicatively couple the second and third bias voltages during startup, where, enabled by said first start-up branch, said second switch ensures current flow in said second start-up branch. 11. The device of claim 10 further comprising a resistor communicatively coupled between the first cascode current mirror and a voltage supply. 12. The device of claim 10 wherein the first and second switches are transistors. 13. The device of claim 10 wherein the startup circuit further comprises a timing means operable to control the timing of the first and second switches. 14. The device of claim 13 wherein the timing means comprises a transistor and a capacitor. 15. The device of claim 10 wherein the first cascode current mirror comprises first, second, third, fourth, and fifth transistors, wherein the first and second transistors are cascode-stacked, wherein the third and fourth transistors are cascode-stacked, wherein the gates of the first and third transistors are communicatively coupled to the drain of the second transistor and correspond to the first bias voltage, wherein the fifth transistor is diode-connected, and wherein the drain and gate of the fifth transistor is communicatively coupled to the gates of the second and fourth transistors and correspond to the second bias voltage. 16. The device of claim 15 further comprising a resistor communicatively coupled between the source of the third transistor and a voltage source. 17. The device of claim 10 wherein the second cascode current mirror comprises first, second, third, fourth, and fifth transistors, wherein the first and second transistors are cascode-stacked, wherein the third and fourth transistors are cascode-stacked, wherein the gates of the first and third transistors are communicatively coupled to the drain of the fourth transistor and correspond to the third bias voltage, wherein the fifth transistor is diode-connected, and wherein the drain and gate of the fifth transistor is communicatively coupled to the gates of the second and fourth transistors and correspond to the fourth bias voltage. 18. A method to startup a self-biased reference circuit, said method comprising: providing a first cascode current mirror operable to generate first and second bias voltages in response to a first current and to generate a second current in response to the first and second bias voltages;providing a second cascode current mirror operable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages;communicatively coupling together the first and fourth bias voltages during startup;communicatively coupling together the third bias voltage and an inner drain-source connection in the first cascode current mirror during startup;thereafter uncoupling the first and fourth bias voltages and the third bias voltage and the inner drain-source connection in the first cascode current mirror;providing a start-up circuit comprising a first and a second start-up branch; andensuring current flow in said second start-up branch when enabled by said first start-up branch. 19. The method of claim 18 wherein the steps of communicatively coupling and uncoupling are timed by charging a capacitor. 20. The method of claim 18 wherein the steps of communicatively coupling and uncoupling are accomplished by transistors. 21. A method to startup a self-biased reference circuit, said method comprising: providing a first cascode current mirror operable to generate a first bias voltage in response to a first current, to generate a second bias voltage in response to a fourth current, and to generate a second current in response to the first and second bias voltages;providing a second cascode current mirror operable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages;communicatively coupling together the first and fourth bias voltages during startup;communicatively coupling together the second and third bias voltages during startup;thereafter uncoupling the first and fourth bias voltages and the second and third bias voltages;providing a start-up circuit comprising a first and a second start-up branch; andensuring current flow in said second start-up branch when enabled by said first start-up branch. 22. The method of claim 21 wherein the steps of communicatively coupling and uncoupling are timed by charging a capacitor. 23. The method of claim 21 wherein the steps of communicatively coupling and uncoupling are accomplished by transistors.