Interconnecting initiator devices and recipient devices
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01R-031/08
H04L-012/56
출원번호
US-0498985
(2006-08-04)
등록번호
US-8619554
(2013-12-31)
발명자
/ 주소
Tune, Andrew David
Hotchkiss, Robin
출원인 / 주소
ARM Limited
대리인 / 주소
Nixon & Vanderhye P.C.
인용정보
피인용 횟수 :
0인용 특허 :
6
초록▼
An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at le
An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is operable to provide a data route between said initiator device and said recipient device via said at least two parallel connecting routes and to maintain said data route for the duration of said transaction.
대표청구항▼
1. An interconnect block for a data processing apparatus, said interconnect block providing data routes via which at least one initiator device may access at least three recipient devices, said interconnect block comprising: a first and a second portion;said first portion comprising at least one ini
1. An interconnect block for a data processing apparatus, said interconnect block providing data routes via which at least one initiator device may access at least three recipient devices, said interconnect block comprising: a first and a second portion;said first portion comprising at least one initiator port for communicating with one of said at least one initiator device and at least one recipient port for communicating with one of at least three recipient devices;said second portion comprising at least two recipient ports for communicating with at least two of said at least three recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes;wherein, said first portion comprises: at least two connecting routers associated with said respective at least two parallel connecting routes, andat least one initiator port router associated with said initiator port, said at least one initiator port router configured to perform a transaction in response to a request received from one of said initiator devices at said first portion, said transaction accessing one of said at least three recipient devices and said initiator port router, in response to an address associated with said request, is configured to; provide data routes from said at least one initiator port router to said at least one recipient in response to an address associated with said request indicating said at least one recipient, andprovide data routes from said at least one initiator port router to all of said at least two connecting routers in response to said address indicating one of said at least two recipients communicating with said second portion, and to maintain at least one of said data routes for the duration of said transaction. 2. An interconnect block according to claim 1, wherein said interconnect block is configured to provide said data route via one of said at least two parallel connecting routes, said one of said at least two parallel connecting routes being selected in dependence upon a predetermined criterion. 3. An interconnect block according to claim 1, wherein said at least two parallel connecting routes are equivalent to each other. 4. An interconnect block according to claim 3, wherein said interconnect block is operable to provide said data route via at least two of said at least two parallel connecting routes, one part of said transaction travelling along one of said connecting routes and a further part of said transaction travelling along a different one of said connecting routes. 5. An interconnect block according to claim 1, said interconnect block further comprising at least two connecting routers associated with said respective at least two parallel connecting routes and an arbiter, said arbiter configured to control said at least two connecting routers to select one of said at least two connecting routes for a particular transaction in response to a predetermined criterion. 6. An interconnect block according to claim 5, wherein said arbiter is configured to control said at least two connecting routers, such that said data routes from said initiator port router to said at least two connecting routers associated with said parallel connecting route not selected are closed and a data route to said connecting router associated with said selected connecting route is maintained. 7. An interconnect block according to claim 5, wherein said predetermined criterion comprises an availability of said connecting routes. 8. An interconnect block according to claim 1, wherein said second portion further comprises at least one initiator port for communicating with at least one further initiator device, said second portion configured to provide a data route between said at least one initiator port and said at least two recipient ports, such that said at least one further initiator device may access either of said at least two recipient devices. 9. An interconnect block according to claim 8, said second portion further comprising a further recipient port and said first portion comprising a further initiator port, said further recipient port and said further initiator port being connected to each other such that said interconnect block provides a data route between said at least one further initiator device in communication with said second portion and said at least one recipient device in communication with said first portion. 10. An interconnect block according to claim 1, wherein said first portion comprises at least two initiator ports configured to communicate with at least two initiator devices and wherein said first portion, in response to two requests from two initiator devices, is configured to access two of said at least two recipients received in a same clock cycle from two of said initiator devices, to provide two data routes between said initiator devices and said recipient devices via two of said at least two parallel connecting routes. 11. An interconnect block according to claim 1, comprising two parallel connecting routes.
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이 특허에 인용된 특허 (6)
Olnowich Howard T. (Endwell NY) Bruck Jehoshua (Palo Alto CA) Snir Marc (Briarcliff Manor NY) Upfal Eli (Palo Alto CA), Adaptive switching apparatus for multi-stage networks.
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