최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0693614 (2010-01-26) |
등록번호 | US-8620980 (2013-12-31) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 2 인용 특허 : 299 |
A specialized multiplier block in a programmable device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and output registers to allow c
A specialized multiplier block in a programmable device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and output registers to allow chaining of Direct Form II FIR filters into longer Direct Form II FIR filters. An output accumulator also allows the specialized multiplier block to operate as a time-division multiplexed FIR filter, performing several filtering operations during each clock cycle of the programmable device.
1. A specialized multiplier block for use in a programmable device, said specialized multiplier block comprising: a plurality of multipliers having multiplier inputs;at least one input chain of shift registers, each shift register in said chain of shift registers being of depth n, at least one input
1. A specialized multiplier block for use in a programmable device, said specialized multiplier block comprising: a plurality of multipliers having multiplier inputs;at least one input chain of shift registers, each shift register in said chain of shift registers being of depth n, at least one input of each of said multipliers being connected to said input chain of shift registers;a plurality of adders; andprogrammable connections connecting outputs of said multipliers to inputs of said adders whereby said specialized multiplier block is configurable as an n-channel Direct Form II finite impulse response filter. 2. The specialized multiplier block of claim 1 further comprising: an output register for chaining output of said Direct Form II finite impulse response filter to another said specialized multiplier block; wherein:said specialized multiplier block is configurable with others of said specialized multiplier block as a long n-channel Direct Form II finite impulse response filter. 3. The specialized multiplier block of claim 2 further comprising a selectable output accumulator, said selectable output accumulator including: an adder having an adder input and an adder output;a selectable feedback loop from said adder output to said adder input; anda feedback shift register of depth n in said selectable feedback loop; wherein:said output register is beyond said selectable feedback loop. 4. The specialized multiplier block of claim 2 further comprising a selectable output accumulator, said selectable output accumulator including: an adder having an adder input and an adder output;a selectable feedback loop from said adder output to said adder input; anda feedback shift register of depth n−1 in said selectable feedback loop; wherein:said output register is within said selectable feedback loop. 5. A programmable device comprising the specialized multiplier block of claim 1. 6. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; anda programmable device as defined in claim 5 coupled to the processing circuitry and the memory. 7. A printed circuit board on which is mounted a programmable device as defined in claim 5. 8. The printed circuit board defined in claim 7 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable device. 9. The printed circuit board defined in claim 8 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 10. An integrated circuit device comprising the specialized multiplier block of claim 1. 11. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; andan integrated circuit device as defined in claim 10 coupled to the processing circuitry and the memory. 12. A printed circuit board on which is mounted an integrated circuit device as defined in claim 10. 13. The printed circuit board defined in claim 12 further comprising: memory circuitry mounted on the printed circuit board and coupled to the integrated circuit device. 14. The printed circuit board defined in claim 13 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 15. A specialized multiplier block for use in a programmable device, said specialized multiplier block comprising: a plurality of multipliers having multiplier inputs;at least one input register chain, at least one input of each of said multipliers being connected to said input register chain;a plurality of adders;programmable connections connecting outputs of said multipliers to inputs of said adders whereby said specialized multiplier block is configurable as a Direct Form II finite impulse response filter; andan output register for chaining output of said Direct Form II finite impulse response filter to another said specialized multiplier block; wherein:said specialized multiplier block is configurable with others of said specialized multiplier block as a long Direct Form II finite impulse response filter. 16. The specialized multiplier block of claim 15 further comprising a selectably bypassable register at an input to said input register chain; wherein: said output register is chainable to one said adder of another of said specialized multiplier block; andsaid input register chain is chainable to said input register chain of said another of said specialized multiplier block via said selectably bypassable register of said another of said specialized multiplier block. 17. The specialized multiplier block of claim 15 further comprising a selectable output accumulator; whereby: said specialized multiplier block is configurable as a time-division multiplexed Direct Form II finite impulse response filter. 18. The specialized multiplier block of claim 17 wherein said at least one input of each of said multipliers is selectably connectable to an input other than said input register chain. 19. The specialized multiplier block of claim 18 wherein said input other than said input register chain is programmable logic of said programmable device. 20. A programmable device comprising the specialized multiplier block of claim 15. 21. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; anda programmable device as defined in claim 20 coupled to the processing circuitry and the memory. 22. A printed circuit board on which is mounted a programmable device as defined in claim 20. 23. The printed circuit board defined in claim 22 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable device. 24. The printed circuit board defined in claim 23 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 25. An integrated circuit device comprising the specialized multiplier block of claim 15. 26. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; andan integrated circuit device as defined in claim 25 coupled to the processing circuitry and the memory. 27. A printed circuit board on which is mounted an integrated circuit device as defined in claim 25. 28. The printed circuit board defined in claim 27 further comprising: memory circuitry mounted on the printed circuit board and coupled to the integrated circuit device. 29. The printed circuit board defined in claim 28 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 30. A specialized multiplier block for use in a programmable device, said specialized multiplier block comprising: a plurality of multipliers having multiplier inputs;at least one input register chain, at least one input of each of said multipliers being connected to said input register chain;a plurality of adders;programmable connections connecting outputs of said multipliers to inputs of said adders whereby said specialized multiplier block is configurable as a Direct Form II finite impulse response filter; andan output accumulator selectably connectable to output of said adders; whereby:said specialized multiplier block is configurable as a time-division multiplexed Direct Form II finite impulse response filter. 31. A programmable device comprising the specialized multiplier block of claim 30. 32. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; anda programmable device as defined in claim 31 coupled to the processing circuitry and the memory. 33. A printed circuit board on which is mounted a programmable device as defined in claim 31. 34. The printed circuit board defined in claim 33 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable device. 35. The printed circuit board defined in claim 34 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 36. An integrated circuit device comprising the specialized multiplier block of claim 30. 37. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; andan integrated circuit device as defined in claim 36 coupled to the processing circuitry and the memory. 38. A printed circuit board on which is mounted an integrated circuit device as defined in claim 36. 39. The printed circuit board defined in claim 38 further comprising: memory circuitry mounted on the printed circuit board and coupled to the integrated circuit device. 40. The printed circuit board defined in claim 39 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.
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