[특허]Adhesive/spacer island structure for multiple die package

[미국특허] Adhesive/spacer island structure for multiple die package 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/44 H01L-021/48
출원번호	US-0530841 (2006-09-11)
등록번호	US-8623704 (2014-01-07)
발명자 / 주소	Lee, Sang Ho Ju, Jong Wook Kwon, Hyeog Chan
출원인 / 주소	CHIPPAC, Inc.
대리인 / 주소	Ishimaru & Associates LLP
인용정보	피인용 횟수 : 2 인용 특허 : 135

초록 ▼

An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.

대표청구항 ▼

1. A method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: connecting a wire between a bond pad of a first die and a substrate with the wire having a wire loop height extending from the bond pad;selecting an adhesive/spacer material having pliable spacer elements within an adhesive;depositing the adhesive/spacer material onto a first surface of the first die, the adhesive/spacer material covering 20-50 percent of the first surface of the first die;providing an electrically non-conductive second surface of a second die with a dielectric layer;locating the second surface of the second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: securing the first and second die to one another at the chosen separation; andencapsulating the first die, the second die, and the adhesive/spacer material with an encapsulating material of a filled epoxy containing 80-90 percent filler material. 2. The method according to claim 1 wherein the selecting step includes choosing spacer elements having the same size and shape. 3. The method according to claim 1 wherein the depositing step is carried out to create a plurality of generally equal-size islands of the adhesive/spacer material after the securing step. 4. The method according to claim 1 wherein the depositing step is carried out to create at least three generally equal-size islands of the adhesive/spacer material after the securing step. 5. A method for creating a multiple-die semiconductor chip package, the method comprising: mounting a first die to a substrate, the first die having a first surface with bond pads at the first surface;connecting the bond pads and the substrate with wires, having heights within a wire loop height extending from the bond pads;selecting an adhesive/spacer material comprising pliable spacer elements within an adhesive;depositing the adhesive/spacer material onto a first surface of the first die;providing an electrically non-conductive second surface of a second surface of a second die with a dielectric layer;locating a second surface of the second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; andsecuring the first and second die to one another at a chosen separation to create a multiple-die subassembly with the adhesive/spacer material occupying a first percentage of 20-50 percent of the die bonding region; andencapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, the encapsulating material of a filled epoxy containing 80-90 percent filler material, and the wires within the die bonding region occupying a third percentage of the die bonding region. 6. The method according to claim 5 wherein depositing the adhesive/spacer material includes depositing multiple adhesive/spacer islands of different sizes. 7. The method according to claim 5 wherein the depositing step includes depositing continuous expanses of adhesive/spacer material so that the first percentage is at most about 50 percent. 8. The method according to claim 5 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region. 9. A method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: connecting a wire between a bond pad of a first die and a substrate with the wire having a wire loop height extending from the bond pad;selecting an adhesive/spacer material having pliable spacer elements within an adhesive;choosing an amount of the adhesive/spacer material;depositing the chosen amount of the adhesive/spacer material onto a first surface of the first die, the adhesive/spacer material covering 20-50 percent of the first surface of the first die;providing an electrically non-conductive second surface of a second die with a dielectric layer;locating the second surface of the second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces;securing the first and second die to one another at the chosen separation; andencapsulating the first die, the second die, and the adhesive/spacer material with an encapsulating material of a filled epoxy containing 80-90 percent filler material. 10. The method according to claim 9 wherein depositing the adhesive/spacer material includes depositing multiple adhesive/spacer islands of different sizes. 11. The method according to claim 9 wherein the choosing step is carried out so that the adhesive/spacer material occupies about 20-50% of the die bonding region. 12. A method for creating a multiple-die semiconductor chip package, the method comprising: mounting a first die to a substrate, the first die comprising a first surface with bond pads at the first surface;connecting the bond pads and the substrate with wires, having heights within a wire loop height extending from the bond pads;selecting an adhesive/spacer material having pliable spacer elements within an adhesive;depositing the adhesive/spacer material onto a first surface of the first die to for a non-convex continuous expanse;locating an electrically non-conductive second surface of a second die having a dielectric layer thereon opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: defining a die bonding region between the first and second surfaces; andsecuring the first and second die to one another at a chosen separation to create a multiple-die subassembly with a first percentage of 20-50 percent of the die bonding region occupied by the adhesive/spacer material; andencapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, the encapsulating material of a filled epoxy containing 80-90 percent filler material, and the wires within the die bonding region occupying a third percentage of the die bonding region. 13. The method according to claim 12 wherein depositing the adhesive/spacer material includes depositing multiple adhesive/spacer islands of different sizes. 14. The method according to claim 12 wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.

이 특허에 인용된 특허 (135) 인용/피인용 타임라인 분석

He, Xiping; Dominic, Christopher J., Adhesive wafers for die attach application.
상세보기
Korleski Joseph E., Adhisive-filler polymer film composite.
상세보기
Syed Sajid Ahmad, Apparatus for applying viscous materials to a lead frame.
상세보기
Derderian, James M., Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods.
상세보기
Makoto Terui JP, BGA package and method for fabricating the same.
상세보기
Fee, Setho Sing; Chye, Lim Thiam; Heppler, Steven W.; Yin, Leng Nam; Tan, Keith; Guay, Patrick; Tian, Edmund Lua Koon; Eng, Yap Kah; Seng, Eric Tan Swee, Ball grid array interposer, packages and methods.
상세보기
Kaul Sunil (Fremont CA) Laird Douglas A. (Los Gatos CA), Ball grid array packages for high speed applications.
상세보기
Koopmans, Michel, Bumping technology in stacked die configurations.
상세보기
Culnane Thomas Moran ; Gaynes Michael Anthony ; Seto Ping Kwong ; Shaukatullah Hussain, Chip carrier modules with heat sinks attached by flexible-epoxy.
상세보기
Akram, Salman, Chip package with grease heat sink.
상세보기
Shyue Fong Quek MY; Ying Keung Leung SG; Sang Yee Loong SG; Ting Cheong Ang SG, Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection.
상세보기
Heim Craig G. ; Hooker Wade Leslie ; Trivedi Ajit Kumar, Cooling structure for electronic components.
상세보기
Wu, Chi-Chuan; Huang, Chien-Ping, Crack-preventive semiconductor package.
상세보기
Barrow Michael, Custom corner attach heat sink design for a plastic ball grid array integrated circuit package.
상세보기
Shores A. Andrew (Venice CA), Die attach adhesive film, application method and devices incorporating the same.
상세보기
Watson, Michael John, Die attach adhesives for semiconductor applications utilizing a polymeric base material with inorganic insulator particles of various sizes.
상세보기
Choi, Ill Heung, Duel die package.
상세보기
Goller, Bernd; Ofner, Gerald; Thumbs, Josef; Worner, Holger; Hagen, Robert-Christian; Stumpfl, Christian; Wein, Stefan, Electronic component with at least two stacked semiconductor chips and method for fabricating the electronic component.
상세보기
Combs, Edward G.; Sheppard, Robert P.; Pun, Tai Wai; Ng, Hau Wan; Fan, Chun Ho; McLellen, Neil Robert, Enhanced thermal dissipation integrated circuit package.
상세보기
Moden Walter L., Flip chip adaptor package for bare die.
상세보기
Moden, Walter L., Flip chip adaptor package for bare die.
상세보기
Moden, Walter L., Flip chip adaptor package for bare die.
상세보기
Song, Young-Jae; Kwon, Young-Shin; Youm, Kun-Dae; Kim, Young-Soo, Higher-density memory card.
상세보기
Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.
상세보기
Farnworth Warren M. (Boise ID), Inset die lead frame configuration lead frame for a semiconductor device having means for improved busing and die-lead f.
상세보기
Farquhar, Donald Seton; Jimarez, Lisa Jeanine; Klodowski, Michael Joseph; Zimmerman, Jeffrey Alan, Integrated circuit chip carrier assembly.
상세보기
Hisashi Takeda JP, Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board.
상세보기
Song Young-Jae,KRX ; Seo Jeong-Woo,KRX ; Kim Kyung-Seop,KRX, Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and me.
상세보기
Maeda, Takehiko; Tsukano, Jun, Light thin stacked package semiconductor device and process for fabrication thereof.
상세보기
Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.
상세보기
Lee Shaw Wei (San Jose CA), Maximized substrate design for grid array based assemblies.
상세보기
Nguyen Luu ; Prabhu Ashok ; Kelkar Nikhil ; Takiar Hem P., Method and apparatus for forming a plastic chip on chip package module.
상세보기
Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.
상세보기
Koopmans, Michel, Method of fabricating stacked die configurations utilizing redistribution bond pads.
상세보기
Glenn, Thomas P.; Smith, Lee J.; Zoba, David A.; Ramakrishna, Kambhampati; DiCaprio, Vincent, Method of making a semiconductor package including stacked semiconductor dies.
상세보기
Tomihara, Seiichi, Method of manufacturing a semiconductor device having flexible wiring substrate.
상세보기
Kakimoto Noriko,JPX ; Suematsu Eiji,JPX, Millimeter wave semiconductor device.
상세보기
Pu, Han-Ping; Huang, Chih-Ming; Huang, Chien-Ping, Module device of stacked semiconductor packages and method for fabricating the same.
상세보기
Michael B. Ball, Multi-chip device utilizing a flip chip and wire bond assembly.
상세보기
Jao Jui-Meng,TWX ; Ko Eric,TWX ; Liu Vicky,TWX, Multi-chip integrated circuit package structure for central pad chip.
상세보기
Ming-Hsun Lee TW; Chin-Te Chen TW, Multi-chip module.
상세보기
Vaiyapuri Venkateshwaran,SGX ; Yang Jicheng,SGX, Multi-chip module with stacked dice.
상세보기
Liu,Cheng Cheng, Multi-chip package combining wire-bonding and flip-chip configuration.
상세보기
Kao-Yu Hsu TW; Su Tao TW, Multichip module.
상세보기
Liu, Chung-Lun; Chang, Chin-Huang, Multichip module.
상세보기
Fogal Rich (Boise ID) Ball Michael B. (Boise ID), Multichip module having a stacked chip arrangement.
상세보기
Lin Chun Hung,TWX, Multichip module having stacked chip arrangement.
상세보기
Michii, Kazunari; Akiyama, Tatsuhiko, Multiple chip package semiconductor device.
상세보기
Salman Akram, Multiple die stack apparatus employing T-shaped interposer elements.
상세보기
Lo, Randy H. Y.; Huang, Chien-Ping; Wu, Chi-Chuan, Multiple stacked-chip packaging structure.
상세보기
Chaudhuri, Arun K.; Workman, Derek B.; Walsh, Matthew R., No-flow underfill material and underfill method for flip chip devices.
상세보기
Jeansonne Jeff K., Opposed ball grid array mounting.
상세보기
Shim, Il Kwon; Chow, Seng Guan; Balanon, Gerry, PBGA substrate for anchoring heat sink.
상세보기
Junichi Asada JP, Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same.
상세보기
Chen, Jian-Cheng; Hsiao, Wei-Min, Package of a chip with beveled edges.
상세보기
Chye, Lim Thiam; Fee, Setho Sing; Seng, Eric Tan Swee, Packaged microelectronic component assemblies.
상세보기
Ziegler James F., Process for fabricating single crystal resonant devices that are compatible with integrated circuit processing.
상세보기
Hsu, Chi-Hsing, Quad flat no-lead chip carrier.
상세보기
Uchida, Yasufumi; Saeki, Yoshihiro, Rearrangement sheet, semiconductor device and method of manufacturing thereof.
상세보기
Belgacem Haba ; Donald V. Perino ; Sayeh Khalili, Redistributed bond pads in stacked integrated circuit die package.
상세보기
Ichinose, Michihiko; Takizawa, Tomoko; Honda, Hirokazu; Kata, Keiichirou, Resin-encapsulated semiconductor device.
상세보기
Kondo, Takashi; Bando, Koji; Shibata, Jun; Narutaki, Kazuko, Resin-sealed chip stack type semiconductor device.
상세보기
Benenati Joseph A. ; Bertin Claude L. ; Chen William T. ; Dinan Thomas E. ; Ellis Wayne F. ; Howell Wayne J. ; Knickerbocker John U. ; Pierson Mark V. ; Tonti William R. ; Zalesinski Jerzy M., Rolling ball connector.
상세보기
Hideki Ishii JP; Kazunari Michii JP; Jun Shibata JP; Moriyoshi Nakashima JP, Semiconductor device.
상세보기
Ichikawa, Sunji, Semiconductor device.
상세보기
Ozawa Kaname,JPX ; Okuda Hayato,JPX ; Hiraoka Tetsuya,JPX ; Sato Mitsutaka,JPX ; Akashi Yuji,JPX ; Okada Akira,JPX ; Harayama Masahiko,JPX, Semiconductor device.
상세보기
Tadashi Komiyama JP, Semiconductor device.
상세보기
Terui, Makoto, Semiconductor device.
상세보기
Kurita, Yoichiro; Shironouchi, Toshiaki; Tetsuka, Takashi, Semiconductor device and method for manufacturing the same.
상세보기
Ohuchi Shinji,JPX ; Yamada Shigeru,JPX ; Shiraishi Yasushi,JPX, Semiconductor device and method for manufacturing the same.
상세보기
Nakayama, Hirohisa; Taniguchi, Jun; Abe, Takashi; Nakayama, Toshinori, Semiconductor device and method of fabricating the same, circuit board, and electronic equipment.
상세보기
Emoto, Yoshiaki, Semiconductor device and method of making the same, circuit board and electronic equipment.
상세보기
Ichinose, Michihiko, Semiconductor device and packaging method thereof.
상세보기
Jiang, Tongbi; Fee, Setho Sing; Yean, Tay Wuu; Chye, Lim Thiam, Semiconductor device assemblies and packages including multiple semiconductor devices and methods.
상세보기
Fumihiko Taniguchi JP; Akira Takashima JP, Semiconductor device having an interconnecting post formed on an interposer within a sealing resin.
상세보기
Uchida, Yasufumi, Semiconductor device having multi-chip package.
상세보기
Fogal Rich (Boise ID) King Jerrold L. (Boise ID) Moden Walter L. (Boise ID), Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic cov.
상세보기
Tamaki Kazuo,JPX ; Saza Yasuyuki,JPX ; Dotta Yoshihisa,JPX, Semiconductor device using a chip scale package.
상세보기
Mori Ryuichiro,JPX, Semiconductor module comprising semiconductor packages.
상세보기
Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package.
상세보기
Karnezos, Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages.
상세보기
Karnezos,Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages.
상세보기
Karnezos, Marcos, Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield.
상세보기
Karnezos, Marcos, Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages.
상세보기
Karnezos,Marcos, Semiconductor multipackage module including processor and memory package assemblies.
상세보기
Liao, Chih-Chin; Pu, Han-PIng; Huang, Chien-Ping, Semiconductor package.
상세보기
Tzu Chung-Hsing,TWX, Semiconductor package having multi-dies.
상세보기
Thomas P. Glenn ; Lee J. Smith ; David A. Zoba ; Kambhampati Ramakrishna ; Vincent DiCaprio, Semiconductor package including stacked semiconductor dies and bond wires.
상세보기
Huang, Chien-Ping, Semiconductor package with flash-proof device.
상세보기
Akram, Salman; Brooks, Jerry M., Semiconductor package with stacked substrates and multiple semiconductor dice.
상세보기
Karnezos,Marcos, Semiconductor stacked multi-package module having inverted second package.
상세보기
Karnezos, Marcos, Semiconductor stacked multi-package module having inverted second package and electrically shielded first package.
상세보기
Lin Paul T. (Austin TX), Shielded liquid encapsulated semiconductor device and method for making the same.
상세보기
Takahashi Nobuaki,JPX ; Kyougoku Yoshitaka,JPX ; Hashimoto Katsumasa,JPX ; Miyazaki Shinichi,JPX, Shock resistant semiconductor device and method for producing same.
상세보기
De Givry Jacques (Les Loges En Josas FRX), Solid state memory modules and memory devices including such modules.
상세보기
Yang,Chaur Chin; Wang,Hsueh Te, Stack type flip-chip package.
상세보기
Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.
상세보기
Tao Su,TWX ; Lo Kuang-Lin,TWX ; Chou Kuang-Chun,TWX ; Chen Shih-Chih,TWX, Stacked chip assembly utilizing a lead frame.
상세보기
McMahon, John F., Stacked chip packaging.
상세보기
Levardo, Melvin N.; Gonzales, Marcelo S., Stacked dice standoffs.
상세보기
Lo, Wai Yew; Aripin, Azhar Bin; Tiu, Kong Bee, Stacked die semiconductor device.
상세보기
Akram Salman, Stacked leads-over chip multi-chip module.
상세보기
Mess, Leonard E.; Brooks, Jerry M.; Corisis, David J., Stacked mass storage flash memory package.
상세보기
Corisis, David J., Stacked microelectronic dies and methods for stacking microelectronic dies.
상세보기
Degani, Yinon; Dudderar, Thomas Dixon; Sun, Liguo; Zhao, Meng, Stacked module package.
상세보기
Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.
상세보기
Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Nishimura, Takao, Stacked semiconductor device and method of producing the same.
상세보기
Kikuma, Katsuhito; Ikeda, Mitsutaka; Tsukidate, Yoshihiro; Akashi, Yuji; Ozawa, Kaname; Takashima, Akira; Uno, Tadashi; Nishimura, Takao; Ando, Fumihiko; Onodera, Hiroshi; Okuda, Hayato, Stacked semiconductor device and method of producing the same.
상세보기
St. Amand, Roger D.; Perelman, Vladimir, Stacked semiconductor die assembly having at least one support.
상세보기
Baek, Joong-hyun; Lee, Jin-yang; Im, Yun-hyeok; Lee, Tae-koo, Stacked semiconductor module and method of manufacturing the same.
상세보기
Pedron, Jr., Serafin P., Stacked semiconductor package and method of manufacturing the same.
상세보기
Jichen Wu TW; Meng Ru Tsai TW; Nai Hua Yeh TW; Chen Pin Peng TW, Stacked structure of semiconductor means and method for manufacturing the same.
상세보기
St. Amand,Roger D.; Kim,InTae; Perelman,Vladimir, Stacked-die extension support structure and method thereof.
상세보기
Pu, Han-Ping; Lo, Randy H. Y.; Her, Tzong-Dar; Huang, Chien-Ping; Hsiao, Cheng-Shiu; Wu, Chi-Chuan, Stacked-die package structure.
상세보기
Corbett Tim J. ; Moden Walter L., Structure for attaching a semiconductor wafer section to a support.
상세보기
Her, Tzong-Dar; Lo, Randy H. Y.; Huang, Chien-Ping, Structure of a multi chip module having stacked chips.
상세보기
Wen Chuan Chen TW; Kuo Feng Peng TW; Jichen Wu TW; Chia Jung Chang TW, Structure of stacked integrated circuits.
상세보기
Hoffman, Paul Robert; Zoba, David Albert, Structures for improving heat dissipation in stacked semiconductor packages.
상세보기
Halahan, Patrick B., Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity.
상세보기
Hur, Hyeong Ryeol; Bathan, Henry D.; Camacho, Zigmund R., System for semiconductor package with stacked dies.
상세보기
Nguyen, Luu Thanh; Pham, Ken; Deane, Peter; Mazotti, William Paul; Roberts, Bruce Carlton; Liu, Jia, Techniques for joining an opto-electronic module to a semiconductor package.
상세보기
Nguyen,Luu Thanh; Pham,Ken; Deane,Peter; Mazotti,William Paul; Roberts,Bruce Carlton; Liu,Jia, Techniques for joining an opto-electronic module to a semiconductor package.
상세보기
Rostoker Michael D. (Boulder Creek CA), Techniques for providing high I/O count connections to semiconductor dies.
상세보기
Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
상세보기
Chen, Eing-Chieh; Lai, Cheng-Yuan; Tien, Tzu-Yi, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
상세보기
Eing-Chieh Chen TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW, Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same.
상세보기
Hawke Robert E.,CAX ; Patel Atin J.,CAX ; Binapal Sukhminder S.,CAX ; Divita Charles,CAX ; McNeil Lynn,CAX ; Fletcher Thomas G.,CAX, Three dimensional packaging configuration for multi-chip module assembly.
상세보기
Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
상세보기
Massit Claude (Ismier FRX) Nicolas Grard (Voreppe FRX), Three-dimensional multichip module.
상세보기
Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.
상세보기

이 특허를 인용한 특허 (2) 인용/피인용 타임라인 분석

Lee, Kunsil, Semiconductor package.
상세보기
Lee, Kunsil, Semiconductor package.
상세보기

활용도 분석정보

상세보기

다운로드

내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

[미국특허] Adhesive/spacer island structure for multiple die package 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허에 인용된 특허 (135) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (2) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

연합인증

[미국특허] Adhesive/spacer island structure for multiple die package 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허에 인용된 특허 (135) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (2) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허 더보기

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

활용도 Top5 특허