Heating plate with diode planar heater zones for semiconductor processing
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H05B-003/68
H05B-003/02
출원번호
US-0237444
(2011-09-20)
등록번호
US-8624168
(2014-01-07)
발명자
/ 주소
Gaff, Keith William
Comendant, Keith
출원인 / 주소
Lam Research Corporation
대리인 / 주소
Buchanan Ingersoll & Rooney PC
인용정보
피인용 횟수 :
23인용 특허 :
55
초록▼
A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heate
A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heater zone uses at least one diode as a heater element. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic or polymer sheets having planar heater zones, power supply lines, power return lines and vias.
대표청구항▼
1. A heating plate for a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus, the heating plate comprising: an electrically insulating layer comprising upper and lower electrically insulating layers;planar heater zones comprising at least firs
1. A heating plate for a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus, the heating plate comprising: an electrically insulating layer comprising upper and lower electrically insulating layers;planar heater zones comprising at least first, second, third and fourth planar heater zones, each comprising one or more diodes as heater elements, the planar heater zones located between the upper and lower electrically insulating layers, laterally distributed across the electrically insulating layer and operable to tune a spatial temperature profile on the semiconductor substrate;power supply lines comprising at least a first electrically conductive power supply line electrically connected to anodes of the one or more diodes of the first and second planar heater zones and a second electrically conductive power supply line electrically connected to anodes of the one or more diodes of the third and fourth planar heater zones;power return lines comprising at least a first electrically conductive power return line electrically connected to cathodes of the one or more diodes of the first and third planar heater zones and a second electrically conductive power return line electrically connected to cathodes of the one or more diodes of the second and fourth planar heater zones. 2. The heating plate of claim 1, wherein the planar heater zones do not comprise any resistive heater elements. 3. The heating plate of claim 1, wherein (a) the power supply lines and the power return lines are embedded in the electrically insulating layer; the diodes of the planar heater zones are bonded to an upper surface of the lower electrically insulating layer; the power supply lines and the power return lines are electrically connected to the planar heater zones by vias extending vertically through the heating plate; or(b) the power supply lines are embedded in the electrically insulating layer; the power return lines are on an upper surface of the electrically insulating layer; the diodes of the planar heater zones are bonded to the upper surface of the lower electrically insulating layer; the power return lines are electrically connected to the planar heater zones laterally and the power supply lines are electrically connected to the planar heater zones by vias extending vertically through the heating plate. 4. The heating plate of claim 1, wherein the planar heater zones are sized such that: (a) each planar heater zone is not larger than four device dies being manufactured on the semiconductor substrate, or(b) each planar heater zone is not larger than two device dies being manufactured on the semiconductor substrate, or(c) each planar heater zone is not larger than one device die being manufactured on the semiconductor substrate, or(d) each planar heater zone is scaled with sizes of device dies on the semiconductor substrate and the overall size of the semiconductor substrate. 5. The heating plate of claim 1, wherein the planar heater zones are sized such that: (a) each planar heater zone is 0.1 to 1 cm2, or(b) each planar heater zone is 2 to 3 cm2, or(c) each planar heater zone is 1 to 15 cm2. 6. The heating plate of claim 1, wherein the heating plate includes 100 to 700 planar heater zones. 7. The heating plate of claim 1, wherein the electrically insulating layer comprises a polymer material, a ceramic material, a fiberglass composite, or a combination thereof. 8. The heating plate of claim 1, wherein the total number of the power supply lines and the power return lines is equal to or less than the total number of the planar heater zones. 9. The heating plate of claim 1, wherein a total area of the planar heater zones is from 50% to 99% of an upper surface of the heating plate. 10. The heating plate of claim 1, wherein the planar heater zones are arranged in a rectangular grid, hexagonal grid or concentric rings; and the planar heater zones are separated from each other by gaps at least 1 millimeter in width and at most 10 millimeters in width. 11. A substrate support assembly comprising: an electrostatic chuck (ESC) including at least one electrostatic clamping electrode configured to electrostatically clamp a semiconductor substrate on the substrate support assembly;the heating plate of claim 1; anda cooling plate attached to a lower side of the heating plate by a thermal barrier layer. 12. The substrate support assembly of claim 11, further comprising at least one primary heater layer arranged above or below and the planar heater zones of the heating plate, wherein the primary heater layer is electrically insulated from the planar heater zones, the power supply lines, and the power return lines of the heating plate; the primary heater layer includes at least one heater which provides mean temperature control of the semiconductor substrate; the planar heater zones provide radial and azimuthal temperature profile control of the semiconductor substrate, during processing thereof. 13. A method for manufacturing the heating plate of claim 1, comprising: pressing a mixture of ceramic powder, binder and liquid into sheets;drying the sheets;forming vias in the sheets by punching holes therein;forming the power supply lines and power return lines on the sheets;aligning the sheets;bonding the sheets by adhesive or sintering to form the upper sheet of the electrically insulating layer;filling the vias with a slurry of conducting powder;bonding diodes onto a lower surface of the upper sheet of the electrically insulating layer such that diode(s) in each planar heater zone are connected to a pair of power supply line and power return line and no two diodes in different planar heater zones share the same pair of power supply line and power return line. 14. The method of claim 13, wherein the power supply lines and power return lines are formed by screen printing a slurry of conducting powder, pressing a precut metal foil, or spraying a slurry of conducting powder. 15. A method for manufacturing the heating plate of claim 1, comprising: (a) bonding a metal sheet onto a fiberglass composite plate, or a metal plate covered by an electrically insulating polymer film;(b) applying a patterned resist film to the surface of the metal sheet wherein the openings in the patterned resist film define the shapes and positions of a group of power lines;(c) forming the group of power lines by chemically etching portions of the metal sheet exposed through the openings in the patterned resist film;(d) removing the resist film;(e) applying an electrically insulating polymer film on the metal sheet;(f) optionally repeat steps (b)-(e) one or more times to form the lower layer of the electrically insulating layer;(g) forming vias by punching holes through the metal sheet(s) and the electrically insulating polymer film(s) and filling the holes with a slurry of conducting powder;(h) bonding diodes, and optionally forming a group of power lines, onto an exposed surface of the topmost electrically insulating polymer film such that diodes in each planar heater zone are connected to a pair of a power supply line and a power return line, and that no two diodes in different planar heater zones share the same pair of power supply line and power return line. 16. A method for plasma processing semiconductor substrates in a plasma processing chamber containing the substrate support assembly of claim 11, comprising: (a) loading a semiconductor substrate into the processing chamber and positioning the semiconductor substrate on the substrate support assembly;(b) determining a temperature profile that compensates for processing conditions affecting critical dimension (CD) uniformity;(c) heating the semiconductor substrate to conform to the temperature profile using the substrate support assembly;(d) igniting plasma and processing the semiconductor substrate while controlling the temperature profile by independently controlled heating of the planar heater zones;(e) unloading the semiconductor substrate from the processing chamber and repeating steps (a)-(e) with a different semiconductor substrate. 17. The substrate support assembly of claim 12, wherein the primary heater layer includes two or more heaters.
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