A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion
A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.
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1. A semiconductor device, comprising: a semiconductor substrate;a dielectric layer overlying the semiconductor substrate;a copper-containing layer formed in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion;a first barrier layer formed between the fi
1. A semiconductor device, comprising: a semiconductor substrate;a dielectric layer overlying the semiconductor substrate;a copper-containing layer formed in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion;a first barrier layer formed between the first portion of the copper-containing layer and the dielectric layer; anda second barrier layer formed at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer;wherein, the first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer. 2. The semiconductor device of claim 1, wherein the second barrier layer is a metal oxide layer comprising manganese (Mn). 3. The semiconductor device of claim 1, wherein the copper-containing layer is formed in a dual damascene opening formed in the dielectric layer, and the dual damascene opening comprises an upper trench section and a lower via-hole section. 4. The semiconductor device of claim 3, wherein the first portion of the copper-containing layer is adjacent a sidewall portion of the upper trench section. 5. The semiconductor device of claim 3, wherein the second portion of the copper-containing layer is adjacent a bottom portion of the upper trench section. 6. The semiconductor device of claim 3, wherein the first portion of the copper-containing layer is adjacent a sidewall portion of the lower via-hole section. 7. The semiconductor device of claim 3, wherein a boundary between the copper-containing layer and a sidewall portion of the upper trench section is free of the second barrier layer, and a boundary between the copper-containing layer and a sidewall portion of the lower via-hole section is free of the second barrier layer. 8. The semiconductor device of claim 1, wherein the dielectric layer comprises a dielectric material layer with a dielectric constant less than 2.5. 9. The semiconductor device of claim 1, further comprising an etch stop layer formed between the semiconductor substrate and the dielectric layer. 10. The semiconductor device of claim 1, wherein the first barrier layer comprises an oxygen-free material. 11. The semiconductor device of claim 1, wherein the first barrier layer comprises at least one of SiN, SiC, or SiCN. 12. A semiconductor device, comprising: a semiconductor substrate;a dielectric layer overlying the semiconductor substrate, wherein an opening comprises an upper trench section and a lower via-hole section and is formed in the dielectric layer, the upper trench section comprises a first sidewall portion and a bottom portion, and the lower via-hole section comprises a second sidewall portion;a copper-containing layer filling the opening formed in the dielectric layer, wherein the copper-containing layer comprises a first portion adjacent the first sidewall portion, a second portion adjacent the bottom portion, and a third portion adjacent the second sidewall portion;a dielectric barrier layer formed between the first portion of the copper-containing layer and the dielectric layer, and formed between the third portion of the copper-containing layer and the dielectric layer; anda metal oxide layer formed at a boundary between the second portion of the copper-containing layer and the dielectric layer, wherein the metal oxide layer is adjacent to an exposed portion of the dielectric layer,wherein a boundary between the first portion of the copper-containing layer and the dielectric barrier layer is free of the metal oxide layer,wherein the metal oxide layer overlays the dielectric barrier layer formed between the third portion of the copper-containing layer and the dielectric layer. 13. The semiconductor device of claim 12, wherein the metal oxide layer comprises manganese (Mn). 14. The semiconductor device of claim 12, wherein the dielectric barrier layer comprises an oxygen-free material. 15. The semiconductor device of claim 12, wherein the dielectric barrier layer comprises at least one of SiN, SiC, or SiCN. 16. The semiconductor device of claim 12, wherein a boundary between the third portion of the copper-containing layer and the dielectric barrier layer is free of the metal oxide layer. 17. A semiconductor device, comprising: a semiconductor substrate;a dielectric layer overlying the semiconductor substrate, wherein an opening comprises an upper trench section and a lower via-hole section in the dielectric layer, the upper trench section comprises a first sidewall portion and a bottom portion, and the lower via-hole section comprises a second sidewall portion;a copper-containing layer in the opening formed in the dielectric layer, wherein the copper-containing layer comprises a first portion adjacent the first sidewall portion, a second portion adjacent the bottom portion, and a third portion adjacent the second sidewall portion;a first barrier layer between the first portion of the copper-containing layer and the dielectric layer, and between the third portion of the copper-containing layer and the dielectric layer; anda second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer, wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer,wherein a boundary between the first portion of the copper-containing layer and the first barrier layer is free of the second barrier layer, and a boundary between the third portion of the copper-containing layer and the first barrier layer is free of the second barrier layer,wherein the first barrier layer between the first portion of the copper-containing layer and the dielectric layer is between a sidewall of the second barrier layer and the dielectric layer. 18. The semiconductor device of claim 17, wherein the first barrier layer comprises an oxygen-free material. 19. The semiconductor device of claim 17, wherein the first barrier layer comprises at least one of SiN, SiC, or SiCN. 20. The semiconductor device of claim 17, wherein a sidewall of the second barrier layer is separated from the first sidewall portion by the first barrier layer.
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이 특허에 인용된 특허 (7)
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