Isolated wire structures with reduced stress, methods of manufacturing and design structures
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/52
H01L-023/48
H01L-029/40
출원번호
US-0734130
(2013-01-04)
등록번호
US-8659173
(2014-02-25)
발명자
/ 주소
Gambino, Jeffrey P.
He, Zhong-Xiang
Lee, Tom C.
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Kotulak, Richard M.
인용정보
피인용 횟수 :
0인용 특허 :
14
초록▼
An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further inclu
An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.
대표청구항▼
1. A method of manufacturing a structure, comprising: forming adjacent wiring structures on a same level, with a space therebetween;forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures;forming a pho
1. A method of manufacturing a structure, comprising: forming adjacent wiring structures on a same level, with a space therebetween;forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures;forming a photosensitive material over the capping layer;forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer; andremoving the exposed capping layer. 2. The method of claim 1, wherein the forming of the adjacent wiring structures on a same level comprises: depositing a metal material on a diffusion barrier layer;patterning the metal material to form the space therebetween; andremoving the diffusion barrier layer. 3. The method of claim 1, wherein the metal material is copper formed by an electroplating process. 4. The method of claim 1, wherein the photosensitive material is a positive tone polyimide material deposited using a blanket deposition process. 5. The method of claim 4, wherein the forming of the opening in the positive tone polyimide material comprises exposing the positive tone polyimide material to energy through a patterned mask, which will result in dissolution of portions of the positive tone polyimide material in a developer. 6. The method of claim 5, further comprising hardening the positive tone polyimide material to form a mask. 7. The method of claim 6, wherein the hardening comprising an annealing process. 8. The method of claim 6, wherein the removing the exposed capping layer comprises a reactive ion etching process, using the hardened positive tone polyimide material as the mask. 9. The method of claim 8, wherein the reactive ion etching isolates the adjacent wiring structures. 10. The method of claim 8, wherein the reactive ion etching forms islands of the capping layer. 11. The method of claim 10, wherein the capping layer is SiN or TaN. 12. A method comprising: forming a bond pad and wiring structures in a dielectric layer, at a predetermined level of a structure;forming vias in the dielectric layer, exposing the bond pad and the wiring structures;forming a diffusion barrier layer within the vias and exposed portions of the dielectric layer;forming a metal over the wiring structures, at a higher level of the structure, wherein the forming of the metal comprises: blocking a via over the bond pad; andforming the metal in the vias over the wiring structures and over portions of the diffusion barrier layer adjacent to the vias over the wiring structures;patterning of the metal to form two separate metal wiring structures with a space therebetween;forming a capping layer over the two separate metal wiring structures, including on a surface of the dielectric layer exposed within the space between the two separate metal wiring structures;forming a photosensitive material over the capping layer;forming an opening in the photosensitive material between the two separate metal wiring structures to expose the capping layer; andremoving the exposed capping layer to isolate the two separate metal wiring structures and reduce stress on the structure. 13. The method of claim 12, wherein the metal is copper formed by an electroplating process. 14. The method of claim 12, wherein: the photosensitive material is a positive tone polyimide material; andthe forming of the opening in the positive tone polyimide material comprises exposing the positive tone polyimide material to energy through a patterned mask, which will result in dissolution of portions of the positive tone polyimide material over the bond pad and between the two separate metal wiring structures, during a subsequent develop step. 15. The method of claim 14, further comprising hardening the positive tone polyimide material to form a mask, wherein: the hardening comprises an annealing process; andthe removing the exposed capping layer comprises a reactive ion etching process, using the hardened positive tone polyimide material as the mask. 16. The method of claim 14, wherein the reactive ion etching isolates the two separate metal wiring structures. 17. The method of claim 14, wherein the reactive ion etching forms islands of the capping layer. 18. The method of claim 17, wherein the capping layer is SiN or TaN. 19. A structure, comprising: a bond pad and a plurality of wiring structures formed at a level above a substrate;a plurality of metal wiring structures with a space therebetween, formed at a layer above the plurality of wiring structures and the bond pad, the plurality of metal wiring structures being isolated from one another by a space therebetween;isolated capping layer islands on each of the plurality of wiring structures; anda polyimide material on the isolated capping layer islands, on each of the plurality of wiring structures. 20. The structure of claim 19, wherein the plurality of wiring structures are thick wires on an order of between about 3 μm to about 10 μm. 21. The structure of claim 19, wherein each of the isolated capping layer islands are isolated from each other by a break in capping material within the space between each of the plurality of metal wiring structures. 22. A method in a computer-aided design system for generating a functional design model of a structure with a thick copper wiring layer, the method comprising: generating a functional representation of a bond pad and a plurality of wiring structures formed at a level above a substrate;generating a functional representation of a plurality of metal wiring structures with a space therebetween, formed at a layer above the plurality of wiring structures and the bond pad, the plurality of metal wiring structures being isolated from one another by a space therebetween; andgenerating a functional representation of isolated capping layer islands on each of the plurality of wiring structures; andgenerating a functional representation of a polyimide material on the isolated capping layer islands, on each of the plurality of wiring structures.
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