최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0904134 (2010-10-13) |
등록번호 | US-8661392 (2014-02-25) |
발명자 / 주소 |
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출원인 / 주소 |
|
대리인 / 주소 |
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인용정보 | 피인용 횟수 : 12 인용 특허 : 504 |
A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plura
A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.
1. A semiconductor device, comprising: a plurality of cells, wherein each of the plurality of cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner, and wherein each of the plurality of cells includes circuitry for performing one or more logic functions,
1. A semiconductor device, comprising: a plurality of cells, wherein each of the plurality of cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner, and wherein each of the plurality of cells includes circuitry for performing one or more logic functions, the circuitry including a plurality of conductive features defined in one or more levels of the cell,wherein one or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone, wherein the exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary, wherein the encroachment distance extends from a position corresponding to the inward extent of the exclusion distance from the first segment of the outer cell boundary, to an outermost edge of the encroaching feature relative to an interior of the given cell,wherein the level of the given cell having the encroaching feature is also defined to correspondingly include a spacing allowance region adjacent to a second segment of the outer cell boundary located opposite the given cell from the first segment of the outer cell boundary, wherein the spacing allowance region extends perpendicularly inward into the given cell from the second segment of the outer cell boundary by a spacing allowance distance equal to at least the encroachment distance plus the exclusion distance, wherein the spacing allowance region within the level of the given cell does not include any conductive features. 2. A semiconductor device as recited in claim 1, wherein the encroaching feature is a conductive feature within a gate electrode level of the given cell. 3. A semiconductor device as recited in claim 2, wherein the gate electrode level of the given cell is defined to include only linear-shaped conductive features positioned parallel to each other. 4. A semiconductor device as recited in claim 2, wherein the gate electrode level of the given cell is defined to include arbitrary shaped conductive features, and wherein the encroaching feature includes both a portion that is parallel to the first segment of the outer cell boundary and a portion that is perpendicular to the first segment of the outer cell boundary. 5. A semiconductor device as recited in claim 1, wherein the encroaching feature is a conductive interconnect feature within an interconnect level of the given cell, wherein the interconnect level of the given cell is defined above a gate electrode level of the given cell. 6. A semiconductor device as recited in claim 5, wherein the interconnect level of the given cell is defined to include only linear-shaped conductive features positioned parallel to each other. 7. A semiconductor device as recited in claim 5, wherein the interconnect level of the given cell is defined to include arbitrary shaped conductive features, and wherein the encroaching feature includes both a portion that is parallel to the first segment of the outer cell boundary and a portion that is perpendicular to the first segment of the outer cell boundary. 8. A semiconductor device as recited in claim 1, wherein the outermost edge of the encroaching feature is located inside of the outer cell boundary so as to be located inside of the given cell. 9. A semiconductor device as recited in claim 1, wherein the outermost edge of the encroaching feature is located outside of the outer cell boundary, such that the encroaching feature overlaps the first segment of the outer cell boundary. 10. A semiconductor device as recited in claim 9, wherein the encroaching feature is a linear-shaped conductive feature positioned parallel to the first segment of the outer cell boundary, such that a width direction of the encroaching feature is perpendicular to the first segment of the outer cell boundary, and wherein a first extent of the encroaching feature in the width direction inside of the first segment of the outer cell boundary is equal to a second extent of the encroaching feature in the width direction outside of the first segment of the outer cell boundary. 11. A semiconductor device as recited in claim 9, wherein the encroaching feature is a linear-shaped conductive feature positioned parallel to the first segment of the outer cell boundary, such that a width direction of the encroaching feature is perpendicular to the first segment of the outer cell boundary, and wherein a first extent of the encroaching feature in the width direction inside of the first segment of the outer cell boundary is different from a second extent of the encroaching feature in the width direction outside of the first segment of the outer cell boundary. 12. A semiconductor device as recited in claim 11, wherein a width size of the encroaching feature as measured in the width direction is an odd number defined to cause the first extent of the encroaching feature in the width direction to be different from the second extent of the encroaching feature in the width direction. 13. A semiconductor device as recited in claim 9, wherein the given cell corresponds to a first cell, and wherein the semiconductor device further includes a second cell, wherein the second cell includes a second encroaching feature positioned to overlap a third segment of an outer cell boundary of the second cell, wherein the second encroaching feature of the second cell is shaped to align with the encroaching feature of the first cell when the third segment of the second cell outer boundary is aligned with the first segment of the first cell outer boundary, and wherein the encroaching feature of the first cell and the second encroaching feature of the second cell have a shared functionality such that a single instance of the encroaching feature within the semiconductor device provides the shared functionality for both the first and second cells when the third segment of the second cell outer boundary is aligned with the first segment of the first cell outer boundary. 14. A semiconductor device as recited in claim 1, wherein the semiconductor device includes both the given cell and a mirrored version of the given cell, wherein both the given cell and the mirrored version of the given cell each have a common centerline defined parallel to and equidistant between the first and second segments of the outer cell boundary, and wherein conductive features within the mirrored version of the given cell respectively correspond to conductive features within the given cell having been flipped about the common centerline. 15. A semiconductor device as recited in claim 1, wherein the exclusion distance is based on a design rule distance, wherein the design rule distance is a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device, wherein the design rule distance is within a range extending from about 30 nanometers to about 90 nanometers. 16. A semiconductor device as recited in claim 1, wherein the exclusion distance is based on a design rule distance, wherein the design rule distance is a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device, wherein the design rule distance is less than 70 nanometers. 17. A semiconductor device as recited in claim 1, wherein the exclusion distance is based on a design rule distance, wherein the design rule distance is a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device, wherein the exclusion distance is equal to one-half of the design rule distance.
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