IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
|
| 출원번호 |
US-0483845
(2012-05-30)
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| 등록번호 |
US-8665940
(2014-03-04)
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|
발명자
/ 주소 |
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| 출원인 / 주소 |
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| 대리인 / 주소 |
Silicon Edge Law Group LLP
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| 인용정보 |
피인용 횟수 :
1 인용 특허 :
55 |
초록
▼
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
대표청구항
▼
1. An integrated circuit operable to receive an input signal conveying information symbols, comprising: an equalizer operable to equalize the input signal;a clock recovery circuit operable to generate a recovered clock signal dependent on signal level transitions in the input signal, wherein the sig
1. An integrated circuit operable to receive an input signal conveying information symbols, comprising: an equalizer operable to equalize the input signal;a clock recovery circuit operable to generate a recovered clock signal dependent on signal level transitions in the input signal, wherein the signal level transitions of the input signal express incoming data patterns; andcircuitry operable to control settings of the equalizer dependent on whether edges of the recovered clock signal associated with a subset of the incoming data patterns are early or late relative to the information symbols of the input signal;where the subset of the incoming data patterns only includes one or more worst-case data patterns. 2. The integrated circuit of claim 1, where: the equalizer is operable to equalize the input signal to produce an equalized signal;the clock recovery circuit is operable to generate the recovered clock signal by tracking logic level transitions represented by the equalized signal; andthe circuitry is operable to control the settings dependent on whether the edges of the recovered clock sign are early or late relative to the logic level transitions represented by the equalized signal. 3. The integrated circuit of claim 2, where each symbol is a bit. 4. An integrated circuit operable to receive an input signal conveying information symbols, comprising: an equalizer operable to equalize the input signal;a clock recovery circuit operable to generate a recovered clock signal dependent on signal level transitions in the input signal;circuitry operable to control settings of the equalizer dependent on whether edges of the recovered clock signal are early or late relative to the information symbols of the input signal;where: the equalizer is operable to equalize the input signal to produce an equalized signal;the clock recovery circuit is operable to generate the recovered clock signal by tracking logic level transitions represented by the equalized signal; andthe circuitry is operable to control the settings dependent on whether the edges of the recovered clock sign are early or late relative to the logic level transitions represented by the equalized signal; andwhere the clock recovery circuit comprises an edge sampler and a data sampler, and where the circuitry is operable to receive an edge sample from the edge sample and patterns of symbols from the data sampler, to determine whether early or late status of the edges of the recovered clock signal are correlated with specific patterns of symbols, and to control the settings of the equalizer dependent on whether the early or late status is correlated with the specific patterns of symbols. 5. The integrated circuit of claim 4, where the input signal is a double data rate input signal, where the data sampler is a first data sampler, and where the integrated circuit further comprises a second data sampler, each of the first and second data samplers adapted to sample respective symbols conveyed by the input signal. 6. The integrated circuit of claim 1, where the circuitry is gated and is operable to control settings of the equalizer in a burst-mode. 7. An integrated circuit operable to receive an input signal conveying information symbols, comprising: an equalizer operable to equalize the input signal;a clock recovery circuit operable to generate a recovered clock signal dependent on signal level transitions in the input signal;circuitry operable to control settings of the equalizer dependent on whether edges of the recovered clock signal are early or late relative to the information symbols of the input signal;where: the circuitry is operable to determine whether early or late status of the edges of the recovered clock signal are correlated with specific patterns of symbols;the equalizer is operable to apply a range of amplification factors to equalize the input signal; andthe circuitry is operable to control the settings of the equalizer so as to apply higher amplification factors to higher frequency components of the input signal. 8. An integrated circuit operable to receive an input signal conveying bits of information, comprising: an equalizer operable to equalize the input signal;a clock recovery circuit operable to generate a recovered clock signal dependent on signal level transitions in the input signal; andcircuitry operable to control settings of the equalizer dependent on whether early or late edges of the recovered clock signal are correlated with specific bit patterns of the input signal. 9. The integrated circuit of claim 8, where: the equalizer is operable to equalize the input signal to produce an equalized signal;the clock recovery circuit is operable to generate the recovered clock signal by tracking logic level transitions represented by the equalized signal; andthe circuitry is operable to control the settings dependent on whether the edges of the recovered clock sign are early or late relative to the logic level transitions represented by the equalized signal. 10. The integrated circuit of claim 9, where the clock recovery circuit comprises an edge sampler and a data sampler, and where the circuitry is operable to receive an edge sample from the edge sample and patterns of symbols from the data sampler, to determine whether early or late status of the edges of the recovered clock signal are correlated with specific patterns of symbols, and to control the settings of the equalizer dependent on whether the early or late status is correlated with the specific patterns of symbols. 11. The integrated circuit of claim 10, where the input signal is a double data rate input signal, where the data sampler is a first data sampler, and where the integrated circuit further comprises a second data sampler, each of the first and second data samplers adapted to sample respective bits conveyed by the input signal. 12. An integrated circuit operable to receive an input signal conveying bits of information, comprising: an equalizer operable to equalize the input signal to generate an equalized signal;a circuit operable to generate an edge clock signal dependent on transitions in the equalized signal; anda comparator operable to determine whether transitions in the edge clock signal are early or late relative to the transitions in the equalized signal;wherein the integrated circuit is further operable to adjust equalization provided by the equalizer dependent whether at least one specific bit pattern is correlated with early or late transitions in the edge clock signal relative to the transitions in the equalized signal. 13. The integrated circuit of claim 12, where the edge clock signal is generated to have a frequency corresponding to at least one transition per bit of information of the input signal. 14. The integrated circuit of claim 13, where: the equalizer is operable to equalize the input signal to produce an equalized signal;the circuit operable to generate the edge clock signal is operable to generate the edge clock signal by tracking logic level transitions represented by the equalized signal; andthe circuit is operable to control the equalizer dependent on whether the edges of the edge clock signal are early or late relative to the logic level transitions represented by the equalized signal. 15. The integrated circuit of claim 14, where the circuit operable to generate the edge clock signal comprises an edge sampler and a data sampler, and where the circuit is operable to receive an edge sample from the edge sampler and patterns of symbols from the data sampler, to determine whether early or late status of the edges of the edge clock signal are correlated with specific patterns of symbols, and to control the equalizer dependent on whether the early or late status is correlated with the specific patterns of symbols. 16. The integrated circuit of claim 15, where the input signal is a double data rate input signal, where the data sampler is a first data sampler, and where the integrated circuit further comprises a second data sampler, each of the first and second data samplers adapted to sample respective bits conveyed by the input signal. 17. An integrated circuit operable to receive an input signal conveying bits of information, comprising: an equalizer operable to equalize the input signal to generate an equalized signal;a circuit operable to generate an edge clock signal dependent on transitions in the equalized signal;a comparator operable to determine whether transitions in the edge clock signal are early or late relative to the transitions in the equalized signal; andcircuitry operable to isolate the transitions in the input signal as associated with respective subsets of overall bit patterns conveyed by the equalized signal;wherein the integrated circuit is further operable to dynamically adjust equalization of the input signal by adjusting amplification factors provided by the equalizer for different bit frequencies represented by the input signal, according to whether the respective subsets of overall bit patterns are correlated with early or late transitions in the edge clock signal relative to the transition of the equalized signal. 18. An integrated circuit operable to receive an input signal conveying bits of information, comprising: an equalizer operable to generate an equalized signal from the input signal;a clock recovery circuit operable to generate a recovered clock signal dependent on data samples and edge samples taken from the equalized signal; andmeans for identifying respective patterns of bits conveyed by the input signal, for correlating with the respective patterns of bits whether transitions in the equalized signal are early or late relative to the recovered clock signal, and for adjusting settings of the equalizer equalization of the input signal by adjusting amplification factors provided by according to whether the respective patterns of bits are correlated with early or late transitions in the equalized signal relative to the recovered clock signal relative.
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