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Automatic virtual metrology for semiconductor wafer result prediction 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0025933 (2008-02-05)
등록번호 US-8682466 (2014-03-25)
발명자 / 주소
  • Ko, Francis
  • Lai, Chih-Wei
  • Zuo, Kewei
  • Lo, Henry
  • Wang, Jean
  • Chen, Ping-Hsu
  • Lim, Chun-Hsien
  • Yu, Chen-Hua
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Haynes and Boone, LLP
인용정보 피인용 횟수 : 2  인용 특허 : 64

초록

A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predict

대표청구항

1. A method for semiconductor wafer result prediction, comprising using software and hardware to perform: collecting manufacturing data, including processing tool data from at least one semiconductor manufacturing tool and product data from at least one metrology tool, wherein the product data are c

이 특허에 인용된 특허 (64)

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  53. Kamon,Kazuya, Simulator for a chemical mechanical polishing.
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  57. Shen, Hsueh Chi, System and method for real-time fault detection, classification, and correction in a semiconductor manufacturing environment.
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  59. Kroyan, Armen; Zhang, Youping; Morita, Etsuya; Ligtenberg, Adrianus, System for designing integrated circuits with enhanced manufacturability.
  60. Lin, Chun-Hsien; Ko, Francis; Zuo, Kewei; Lo, Henry; Wang, Jean, System for extraction of key process parameters from fault detection classification to enable wafer prediction.
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이 특허를 인용한 특허 (2)

  1. Vaid, Alok; Saleh, Ned R.; Sendelbach, Matthew J.; Rana, Narender N., Automated hybrid metrology for semiconductor device fabrication.
  2. Lu, Ning, Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types.
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