최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0023796 (2011-02-09) |
등록번호 | US-8686475 (2014-04-01) |
우선권정보 | DE-101 46 132 (2001-09-19); WO-PCT/EP01/11299 (2001-09-30); WO-PCT/EP01/11593 (2001-10-08); DE-101 54 259 (2001-11-05); EP-01129923 (2001-12-14); EP-02001331 (2002-01-18); DE-102 06 653 (2002-02-15); DE-102 06 856 (2002-02-18); DE-102 06 857 (2002-02-18); DE-102 07 224 (2002-02-21); DE-102 07 226 (2002-02-21); DE-102 08 434 (2002-02-27); DE-102 08 435 (2002-02-27); WO-PCT/EP02/02398 (2002-03-05); WO-PCT/EP02/02403 (2002-03-05); WO-PCT/EP02/02404 (2002-03-05); DE-102 12 621 (2002-03-21); DE-102 12 622 (2002-03-21); DE-102 19 681 (2002-05-02); EP-02009868 (2002-05-02); DE-102 27 650 (2002-06-20); DE-102 36 269 (2002-08-07); DE-102 36 271 (2002-08-07); DE-102 36 272 (2002-08-07); DE-102 38 172 (2002-08-21); DE-102 38 173 (2002-08-21); DE-102 38 174 (2002-08-21); DE-102 40 000 (2002-08-27); DE-102 40 022 (2002-08-27); WO-PCT/DE02/03278 (2002-09-03); DE-102 41 812 (2002-09-06); WO-PCT/EP02/10084 (2002-09-09); DE-102 26 186 (2003-06-12) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 2 인용 특허 : 570 |
A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.
1. A Field Programmable Gate Array (FPGA) integrated device comprising: at least two dies that are stacked;a configurable interconnect structure;an arrangement of configurable cells interconnected by the configurable interconnect structure; wherein: at least some of the configurable cells include Ar
1. A Field Programmable Gate Array (FPGA) integrated device comprising: at least two dies that are stacked;a configurable interconnect structure;an arrangement of configurable cells interconnected by the configurable interconnect structure; wherein: at least some of the configurable cells include Arithmetic Logic Units (ALUs);the configurable interconnect structure includes switching elements;the configurable cells are implemented on at least a first one of the at least two dies; andat least parts of an interconnect structure are implemented on at least a second one of the at least two dies. 2. The FPGA integrated device according to claim 1, further comprising at least one dedicated interface unit that interfaces between the programmable data processing units and a device external to the FPGA integrated device. 3. The FPGA integrated device according to claim 2, further comprising at least one dedicated Peripheral Component Interconnect (PCI) unit. 4. The FPGA integrated device according to claim 2, further comprising at least one dedicated Ethernet unit. 5. The FPGA integrated device according to claim 1, wherein at least some of the ALUs are capable of splitting operands into a respective set of data, data of which is processable independently of each other and splitting a result into a respective set of data, data of which is processable independently of each other. 6. The FPGA integrated device according to claim 5, wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately. 7. The FPGA integrated device according to claim 1, wherein at least some of the ALUs are capable of single instruction multiple data (SIMD) processing. 8. The FPGA integrated device according to claim 7, wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately. 9. The FPGA integrated device according to claim 1, wherein at least some switches of the interconnect structure are implemented on the second die. 10. The FPGA integrated device according to claim 1, wherein at least some of the dies are interconnected by vias. 11. The FPGA integrated device according to claim 10, wherein the vias extend through a silicon layer. 12. The FPGA integrated device according to claim 1, wherein the at least parts of the interconnect structure implemented on the at least a second one of the at least two dies includes the configurable interconnect structure. 13. The FPGA Integrated device according to claim 1, wherein the at least parts of the interconnect structure on the at least a second one of the at least two dies comprises switching elements. 14. The FPGA Integrated device according to claim 1, wherein all of the at least two dies in the stack are identical. 15. The FPGA Integrated device according to claim 1, wherein at least some of the dies in the stack are different from other dies that are stacked. 16. The FPGA Integrated device according to claim 1, wherein at least one die in the stack comprises an ALU and at least one die in the stack comprises an input/output component. 17. The FPGA Integrated device according to any one of claims 1, 14, 15 and 16, wherein at least one smaller die is mounted on top of the first die. 18. The FPGA Integrated device according to claim 17, wherein a plurality of dies is mounted on top of the first die. 19. The FPGA Integrated device according to claim 1, wherein a plurality of dies is mounted on top of the first die. 20. The FPGA Integrated device according to claim 19, wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer. 21. The FPGA Integrated device according to any one of claims 1 and 10, wherein at least some of the dies are interconnected by bumps. 22. The FPGA Integrated device according to claim 1, wherein external interfaces are implemented on at least a third die. 23. The FPGA Integrated device according to any one of claims 1 and 22, wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer. 24. The FPGA Integrated device according to claim 23, wherein at least some of the dies are interconnected by bumps. 25. The FPGA Integrated device according to claim 1, wherein the first die comprises wiring. 26. The FPGA Integrated device according to claim 1, wherein the first die comprises solely wiring. 27. The FPGA Integrated device according to claim 1, wherein the first die comprises switching elements. 28. The FPGA Integrated device according to claim 1, wherein the first die comprises switching elements and wiring. 29. A system comprising: at least one processor; andat least one data processing device communicatively coupled to the processor;wherein: the data processing device includes an arrangement of configurable cells interconnected by a configurable interconnect structure;at least some of the configurable cells include Arithmetic Logic Units (ALUs);the configurable interconnect structure includes switching elements;the configurable cells are implemented on at least a first one of at least two dies that are stacked; andat least parts of an interconnect structure are implemented on at least a second one of the at least two dies. 30. The system according to claim 29, wherein the at least one processor and the at least one data processing device are connected via an interface implemented on a die of the data processing device. 31. The system according to claim 29, wherein the at least one data processing device is a Field Programmable Gate Array (FPGA) device. 32. The system according to claim 29, wherein the at least one data processing device comprises Field Programmable Gate Array (FPGA) cells. 33. The system according to claim 29, further comprising at least one interface unit dedicated to the data processing device and that interfaces between the data processing device and a device external to a chip on which the data processing device is positioned. 34. The system according to claim 33, further comprising at least one Peripheral Component Interconnect (PCI) unit dedicated to the data processing device. 35. The system according to claim 31, further comprising at least one Ethernet unit dedicated to the data processing device. 36. The system according to claim 29, wherein at least some of the ALUs are capable of splitting operands into a respective set of data, data of which is processable independently of each other and splitting a result into a respective set of data, data of which is processable independently of each other. 37. The system according to claim 36, wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately. 38. The system according to claim 29, wherein at least some of the ALUs are capable of single instruction multiple data (SIMD) processing. 39. The system according to claim 38, wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately. 40. The system according to claim 29, wherein at least some switches of the interconnect structure are implemented on the second die. 41. The system according to claim 29, wherein at least some of the dies are interconnected by vias. 42. The system according to claim 29, wherein the at least parts of the interconnect structure implemented on the at least a second one of the at least two dies includes the configurable interconnect structure. 43. The system according to claim 29, wherein the at least parts of the interconnect structure on the at least a second one of the at least two dies comprises switching elements. 44. The system according to claim 29, wherein all of the at least two dies in the stack are identical. 45. The system according to claim 29, wherein at least some of the dies in the stack are different from other dies that are stacked. 46. The system according to claim 29, wherein at least one die in the stack comprises an ALU and at least one die in the stack comprises an input/output component. 47. The system according to any one of claims 29, 44, 45 and 46, wherein at least one smaller die is mounted on top of the first die. 48. The system according to claim 47, wherein a plurality of dies is mounted on top of the first die. 49. The system according to claim 29, wherein a plurality of dies is mounted on top of the first die. 50. The system according to claim 49, wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer. 51. The system according to any one of claims 29 and 41, wherein at least some of the dies are interconnected by bumps. 52. The system according to claim 29, wherein external interfaces are implemented on at least a third die. 53. The system according to any one of claims 29 and 52, wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer. 54. The system according to claim 53, wherein at least some of the dies are interconnected by bumps. 55. The system according to claim 29, wherein the first die comprises wiring. 56. The system according to claim 29, wherein the first die comprises solely wiring. 57. The system according to claim 29, wherein the first die comprises switching elements. 58. The system according to claim 29, wherein the first die comprises switching elements and wiring.
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