초록 ▼

In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the fi

In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

대표청구항 ▼

1. A method for redundant data storage across multiple storage devices, the method comprising: storing a collection of data chunks as a plurality of N−1 data stripes across N daughter-memory-cards including non-volatile memory, where N is three or more, wherein each data chunk of up to N data chunks

1. A method for redundant data storage across multiple storage devices, the method comprising: storing a collection of data chunks as a plurality of N−1 data stripes across N daughter-memory-cards including non-volatile memory, where N is three or more, wherein each data chunk of up to N data chunks forming a data stripe is stored in a different daughter-memory-card;storing a parity stripe across the N daughter-memory-cards including N−1 data parity chunks and one meta parity chunk;wherein each Kth daughter-memory-card of N−1 daughter-memory-cards stores a Kth data parity chunk of the N−1 parity chunks computed as parity of up to N data chunks forming the Kth data stripe; andwherein an Nth daughter-memory-card of the N daughter-memory-cards stores the meta parity chunk computed as parity of the N−1 data parity chunks stored in the respective N−1 daughter-memory-cards. 2. The method of claim 1, further comprising: reading a first data stripe of data across the N daughter-memory-cards. 3. The method of claim 2, further comprising: reading the first data parity chunk from the parity stripe in response to reading the first data stripe;computing a first computed parity of the N−1 data chunks forming the first data stripe read; andcomparing the first computed parity with the first data parity chunk. 4. A method for redundant data storage across multiple storage devices, the method comprising: storing a collection of data chunks as a plurality of N−1 data stripes across N daughter-memory-cards including non-volatile memory, where N is three or more, wherein each data chunk of up to N data chunks forming a data stripe is stored in a different daughter-memory-card;storing a parity stripe across the N daughter-memory-cards including N−1 data parity chunks and one meta parity chunk, wherein the N−1 data chunks and the one data parity chunk or meta parity chunk in a daughter-memory-card collectively has a size of one write page into non-volatile memory;reading a first data stripe of data across the N daughter-memory-cardswherein each Kth daughter-memory-card of N−1 daughter-memory-cards stores a Kth data parity chunk of the N−1 parity chunks computed as parity of up to N data chunks forming the Kth data stripe; andwherein an Nth daughter-memory-card of the N daughter-memory-cards stores the meta parity chunk computed as parity of the N−1 data parity chunks stored in the respective N−1 daughter-memory-cards. 5. The method of claim 4, wherein the write page size is four kilobytes. 6. A method for redundant data storage across multiple storage devices, the method, further comprising: storing a collection of data chunks as a plurality of N−1 data stripes across N daughter-memory-cards including non-volatile memory, where N is three or more, wherein each data chunk of up to N data chunks forming a data stripe is stored in a different daughter-memory-card;storing a parity stripe across the N daughter-memory-cards including N−1 data parity chunks and one meta parity chunk,invalidating a data chunk in a data stripe by marking a data chunk in a data stripe invalid, andretaining the previous data in the data chunk for data redundancy until all data chunks in the data stripe are invalid;wherein each Kth daughter-memory-card of N−1 daughter-memory-cards stores a Kth data parity chunk of the N−1 parity chunks computed as parity of up to N data chunks forming the Kth data stripe; andwherein an Nth daughter-memory-card of the N daughter-memory-cards stores the meta parity chunk computed as parity of the N−1 data parity chunks stored in the respective N−1 daughter-memory-cards. 7. The method of claim 4, wherein a daughter-memory-card has failed and the method further comprises: unplugging the failed daughter-memory-card from a socket in a baseboard;plugging a new daughter-memory-card into the socket of the baseboard;configuring the new daughter-memory-card for use within the baseboard;recreating the data chunks of the failed daughter-memory-card in the new daughter-memory-card; andrecreating the data parity chunk or the meta parity chunk of the failed daughter-memory-card in the new daughter-memory-card. 8. The method of claim 1, wherein a first daughter-memory-card has failed and the method further comprises: recreating parity previously stored in the first daughter-memory-card including recreating a first parity chunk by examining the N−2 parity chunks respectively stored in the second through Nth daughter-memory-cards. 9. The method of claim 8, further comprises: recreating data previously stored in the first daughter-memory-card including recreating a first data chunk of a first data stripe by examining the data chunks of the first data stripe stored in the second through Nth daughter-memory-cards and examining the recreated first parity chunk. 10. The method of claim 9, further comprises: recreating an (N−1)th data chunk of an (N−1)th data stripe by examining the data chunks of the (N−1)th data stripe stored in the second through Nth daughter-memory-cards and examining an (N−1)th parity chunk stored in an (N−1)th daughter-memory-card. 11. The method of claim 1, wherein the Nth daughter-memory-card has failed and the method further comprises: recreating data previously stored in the Nth daughter-memory-card including recreating an Nth data chunk of the first data stripe by examining the data chunks of the first data stripe stored in the first through (N−1)th daughter-memory-cards and examining the first parity chunk stored in the first daughter-memory-card. 12. The method of claim 1, wherein the Nth daughter-memory-card has failed and the method further comprises: recreating parity previously stored in the Nth daughter-memory-card including recreating the meta parity chunk by computing the parity of the first through (N−1)th parity chunks respectively stored in the first through (N−1)th daughter-memory-cards. 13. The method of claim 12, further comprises: recreating data previously stored in the Nth daughter-memory-card including recreating each Nth data chunk of the first through (N−1)th data stripes by examining the data chunks of the first through (N−1)th data stripes stored in the first through (N−1)th daughter-memory-cards and examining each respective data parity chunk stored in each first through (N−1)th daughter-memory-cards.