IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0476819
(2006-06-29)
|
등록번호 |
US-8716696
(2014-05-06)
|
우선권정보 |
KR-10-2005-0114957 (2005-11-29) |
발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
Morgan, Lewis & Bockius LLP
|
인용정보 |
피인용 횟수 :
0 인용 특허 :
4 |
초록
▼
A substrate having a thin film transistor includes a buffer layer on a substrate, source and drain electrodes on the buffer layer, a portion of the buffer layer exposed between the source and drain electrodes, a small organic semiconductor layer on the source electrode and the drain electrode, the o
A substrate having a thin film transistor includes a buffer layer on a substrate, source and drain electrodes on the buffer layer, a portion of the buffer layer exposed between the source and drain electrodes, a small organic semiconductor layer on the source electrode and the drain electrode, the organic semiconductor layer contacting the exposed portion of the buffer layer, a gate insulating layer on the organic semiconductor layer, the gate insulating layer having substantially the same size as the organic semiconductor layer, a gate electrode on the gate insulating layer, a passivation layer over the surface of the substrate including the gate electrode; and a pixel electrode on the passivation layer, the pixel electrode electrically connected to the drain electrode.
대표청구항
▼
1. A thin film transistor, comprising: a buffer layer directly on and contacting a surface of a single-layered glass substrate, the buffer layer formed of an inorganic insulating material or an organic insulating material and comprising a flat top surface;source and drain electrodes on the buffer la
1. A thin film transistor, comprising: a buffer layer directly on and contacting a surface of a single-layered glass substrate, the buffer layer formed of an inorganic insulating material or an organic insulating material and comprising a flat top surface;source and drain electrodes on the buffer layer, the source and drain electrodes being spaced apart from each other such that a portion of the buffer layer is exposed to a space between the source and drain electrodes;a small molecule organic semiconductor layer on the source and drain electrodes and contacting the exposed portion of the buffer layer;a gate insulating layer formed of an organic insulating material on the small molecule organic semiconductor layer;a gate electrode on the gate insulating layer;a passivation layer on the gate electrode and comprising a drain contact hole exposing the drain electrode; anda pixel electrode on the passivation layer and contacting the drain electrode through the drain contact hole,wherein the gate insulating layer, the small molecule organic semiconductor layer, and the gate electrode have substantially a same size in lateral dimension,wherein the inorganic insulating material for the buffer layer includes silicon oxynitride (SiOxNy),wherein the source and drain electrodes includes poly ethylene dioxy thiophene: poly styrene sulfonate (PEDOT:PSS),wherein the small molecule organic semiconductor layer is a p-type semiconductor,wherein the organic insulating material for the gate insulating layer includes polyimide, andwherein the buffer layer provides a desirable surface roughness such that the small molecule organic semiconductor layer has a desirable crystallization characteristic. 2. The thin film transistor according to claim 1, wherein the organic insulating material for the buffer layer includes one of poly vinyl pyrrolidone (PVP), polyvinyl alcohol (PVA), benzocyclobutene (BCB) and poly methyl meth acrylate (PMMA). 3. The thin film transistor according to claim 1, wherein the small molecule organic semiconductor layer includes unsubstituted pentacene (C22H14) and substituted pentacene. 4. An array substrate having a thin film transistor, comprising: a buffer layer directly on and contacting a surface of a single-layered glass substrate, the buffer layer formed of an inorganic insulating material or an organic insulating material and comprising a flat top surface;source and drain electrodes on the buffer layer, a portion of the buffer layer exposed between the source and drain electrodes;a small organic semiconductor layer on the source electrode and the drain electrode, the small molecule organic semiconductor layer contacting the exposed portion of the buffer layer;a gate insulating layer formed of an organic insulating material on the small molecule organic semiconductor layer, the gate insulating layer haying substantially a same size as the small molecule organic semiconductor layer;a gate electrode on the gate insulating layer;a passivation layer over the surface of the substrate including the gate electrode, the passivation layer comprising a drain contact hole exposing the drain electrode; anda pixel electrode on the passivation layer, the pixel electrode contacting the drain electrode through the drain contact hole,wherein the gate insulating layer, the small molecule organic semiconductor layer, and gate electrode have substantially a same size in lateral dimension,wherein the inorganic insulating material for the buffer layer includes silicon oxynitride (SiOxNy),wherein the source and drain electrodes includes poly ethylene dioxy thiophene: poly styrene sulfonate (PEDOT:PSS),wherein the small molecule organic semiconductor layer is a p-type semiconductor,wherein the organic insulating material for the gate insulating layer includes polyimide, andwherein the buffer layer provides a desirable surface roughness so that the small molecule organic semiconductor layer has a desirable crystallization characteristic. 5. The substrate according to claim 4, wherein the pixel electrode is electrically connected to the drain electrode via a first contact hole in the passivation layer.
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