Coding architecture for multi-level NAND flash memory with stuck cells
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03M-013/00
G11C-029/00
G06F-011/10
H03M-013/29
H03M-013/35
출원번호
US-0313512
(2008-11-19)
등록번호
US-8719670
(2014-05-06)
발명자
/ 주소
Marrow, Marcus
출원인 / 주소
SK hynix memory solutions inc.
대리인 / 주소
Van Pelt, Yi & James LLP
인용정보
피인용 횟수 :
4인용 특허 :
51
초록▼
A system for decoding data is disclosed. The system includes: an input interface configured to receive data associated with encoded data; a first decoder configured to decode a first subset of the encoded data to obtain a first portion of decoded data; a second decoder configured to decode a second
A system for decoding data is disclosed. The system includes: an input interface configured to receive data associated with encoded data; a first decoder configured to decode a first subset of the encoded data to obtain a first portion of decoded data; a second decoder configured to decode a second subset of the encoded data to obtain a second portion of the decoded data, wherein the second portion includes decoded data not included in the first portion; and an output interface configured to output the decoded data.
대표청구항▼
1. A system for decoding data, comprising: an input interface configured to receive a readback voltage for each of a plurality of cells;a first demapper configured to generate, for each of the plurality of cells, one or more encoded least significant bit (LSB) values for a given cell based at least
1. A system for decoding data, comprising: an input interface configured to receive a readback voltage for each of a plurality of cells;a first demapper configured to generate, for each of the plurality of cells, one or more encoded least significant bit (LSB) values for a given cell based at least in part on the readback voltage for that cell;a first decoder configured to decode the encoded LSB values to obtain one or more decoded LSB values;a second demapper configured to generate, for each of the plurality of cells, one or more encoded most significant bit (MSB) values for a given cell based at least in part on (1) the readback voltage for that cell and (2) the decoded LSB values;a second decoder configured to decode the encoded MSB values to obtain one or more decoded MSB values, wherein the decoded LSB values do not overlap with the decoded MSB values; andan output interface configured to output decoded data, including the decoded LSB values and the decoded MSB values, for each of the plurality of cells. 2. A system as recited in claim 1, wherein the first decoder is a soft decision decoder. 3. A system as recited in claim 1, wherein the second decoder is a hard decision decoder. 4. A system as recited in claim 1, wherein the second decoder comprises a Reed Solomon (RS) decoder. 5. A system as recited in claim 1, wherein the second decoder comprises a Bose, Ray-Chaudhuri, Hocquenghem (BCH) decoder. 6. A system as recited in claim 1, wherein the first decoder comprises a parity check decoder. 7. A system as recited in claim 1, wherein the first decoder comprises a low density parity check (LDPC) decoder. 8. A system as recited in claim 1, wherein the first decoder is associated with a first coding rate and the second decoder is associated with a second coding rate that is different from the first coding rate. 9. A system as recited in claim 8, wherein the first coding rate is lower than the second coding rate. 10. A system as recited in claim 1, wherein the readback voltage for each of the plurality of cells is retrieved from a flash memory. 11. A system as recited in claim 1, wherein the first decoder is configured to decode prior to the second decoder decoding. 12. A system as recited in claim 1, wherein at least one of: (1) the encoded LSB values or (2) the encoded MSB values is Gray code mapped. 13. A method for decoding data, comprising: receiving a readback voltage for each of a plurality of cells;generating, for each of the plurality of cells, one or more encoded least significant bit (LSB) values for a given cell based at least in part on the readback voltage for that cell;decoding the encoded LSB values using a first decoder to obtain a one or more decoded LSB values;generating, for each of the plurality of cells, one or more encoded most significant bit (MSB) values for a given cell based at least in part on (1) the readback voltage for that cell and (2) the decoded LSB values;decoding the encoded MSB values using a second decoder to obtain one or more decoded MSB values, wherein the decoded LSB values do not overlap with the decoded MSB values; andoutputting decoded data, including the decoded LSB values and the decoded MSB values, for each of the plurality of cells. 14. A method as recited in claim 13, wherein the first decoder is a soft decision decoder. 15. A method as recited in claim 13, wherein the second decoder is a hard decision decoder. 16. A method as recited in claim 13, wherein the second decoder comprises a Reed Solomon (RS) decoder. 17. A method as recited in claim 13, wherein the second decoder comprises a Bose, Ray-Chaudhuri, Hocquenghem (BCH) decoder. 18. A method as recited in claim 13, wherein the first decoder comprises a parity check decoder. 19. A method as recited in claim 13, wherein the first decoder comprises a low density parity check (LDPC) decoder. 20. A method as recited in claim 13, wherein the first decoder is associated with a first coding rate and the second decoder is associated with a second coding rate that is different from the first coding rate. 21. A method as recited in claim 13, wherein at least one of: (1) the encoded LSB values or (2) the encoded MSB values is Gray code mapped.
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