IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0047471
(2011-03-14)
|
등록번호 |
US-8719683
(2014-05-06)
|
우선권정보 |
KR-10-2003-0059206 (2003-08-26) |
발명자
/ 주소 |
- Kyung, Gyu-Bum
- Jeong, Hong-Sil
- Kim, Jae-Yoel
- Park, Sung-Eun
- Yang, Kyeong-Cheol
- Myung, Se-Ho
|
출원인 / 주소 |
- Samsung Electronics Co., Ltd
|
대리인 / 주소 |
The Farrell Law Firm, P.C.
|
인용정보 |
피인용 횟수 :
2 인용 특허 :
9 |
초록
▼
A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a fir
A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix.
대표청구항
▼
1. A system for processing a block Low Density Parity Check (LDPC) code, the system comprising: a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part comprising:a first section (B) inc
1. A system for processing a block Low Density Parity Check (LDPC) code, the system comprising: a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part comprising:a first section (B) including a plurality of first permutation matrices,a second section (D) including a second permutation matrix,a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, anda fourth section (E) including a fourth permutation matrix. 2. The system of claim 1, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a matrix according to (E)(T−1)(B)+D conforms to an identity matrix. 3. The system of claim 1, wherein one of the first permutation matrices is arranged in the first block of the first section (B), and the fourth permutation matrix is arranged in the last block of the fourth section (E). 4. The system of claim 1, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code. 5. A method for decoding a block Low Density Parity Check (LDPC) code by a decoding apparatus, the method comprising: decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part comprising:a first section (B) including a plurality of first permutation matrices,a second section (D) including a second permutation matrix,a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, anda fourth section (E) including a fourth permutation matrix. 6. The method of claim 5, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a matrix according to (E)(T−1)(B)+D conforms to an identity matrix. 7. The method of claim 5, wherein one of the first permutation matrices is arranged in the first block of the first section (B), and the fourth permutation matrix is arranged in the last block of the fourth section (E). 8. The method of claim 5, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code. 9. A system for processing a block Low Density Parity Check (LDPC) code, the system comprising: an encoding apparatus for encoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part comprising:a first section (B) including a plurality of first permutation matrices,a second section (D) including a second permutation matrix,a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, anda fourth section (E) including a fourth permutation matrix. 10. The system of claim 9, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a matrix according to (E)(T−1)(B)+D conforms to an identity matrix. 11. The system of claim 9, wherein one of the first permutation matrices is arranged in the first block of the first section (B), and the fourth permutation matrix is arranged in the last block of the fourth section (E). 12. The system of claim 9, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code. 13. A method for encoding a block Low Density Parity Check (LDPC) code by an encoding apparatus, the method comprising: encoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part comprising:a first section (B) including a plurality of first permutation matrices,a second section (D) including a second permutation matrix,a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, anda fourth section (E) including a fourth permutation matrix. 14. The method of claim 13, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a matrix according to (E)(T−1)(B)+D conforms to an identity matrix. 15. The method of claim 13, wherein one of the first permutation matrices is arranged in the first block of the first section (B), and the fourth permutation matrix is arranged in the last block of the fourth section (E). 16. The method of claim 13, wherein the permutation matrices corresponding to each of the first section (B), the second section (D), the third section (T), and the fourth section (E) are configured such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code.
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