초록 ▼

A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the select

A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.

대표청구항 ▼

1. An apparatus, comprising: a plurality of hardware accelerators;a plurality of processing units; anda hardware register accessible by processing elements and hardware accelerators, to enable a processing element to reserve a hardware accelerator, designate ownership of a storage resource for outpu

1. An apparatus, comprising: a plurality of hardware accelerators;a plurality of processing units; anda hardware register accessible by processing elements and hardware accelerators, to enable a processing element to reserve a hardware accelerator, designate ownership of a storage resource for output data, and designate a consumer of data stored in the storage resource, in response to setting a bit in said hardware register, said processing units to send a string of bits to said register to designate hardware accelerators, designate a location to obtain an input to said accelerators, and to designate a location for storage or output from the accelerators. 2. The apparatus of claim 1, further comprising a plurality of processing elements, the plurality of processing elements comprising: an input processing element coupled to the hardware register, the input processing element to receive input data; andan output processing element coupled to the hardware register, the output processing element to transmit data. 3. The apparatus of claim 1, including a selection unit to receive a control command from a processing element using at least one register of the hardware register and the selection unit is to activate the requested hardware accelerator to perform the media processing function according to the received control command. 4. The apparatus of claim 1, including a control unit to identify a processing element having written a control command and the control unit is to set a control bit within a register of the hardware register to indicate when data is available from the requested hardware accelerator for the identified processing element. 5. The apparatus of claim 1, wherein a processing element is to set one or more control bits within a register of the hardware register to identify one or more processing elements to stall the one or more identified processing elements and prohibit execution of instructions by the one or more identified processing elements until data to be used by the identified processing elements is available in one or more registers. 6. The apparatus of claim 1, wherein in response to a control command to at least one register within the hardware register, the requested hardware accelerator is to indicate the requested hardware accelerator is in use. 7. The apparatus of claim 1, wherein setting one or more control bits within a register of the hardware register is to identify one or more processing elements and is to stall the identified one or more processing elements and prohibit execution of instructions until data required by identified one or more processing elements is available in one or more registers. 8. The apparatus of claim 1, wherein the requested hardware accelerator is to perform a sum of absolute differences determination for a video encoding for a motion picture experts group (MPEG) compliant video stream. 9. The apparatus of claim 1, wherein the requested hardware accelerator is to perform variable length code decoding for a motion picture experts group (MPEG) compliant video stream.