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[미국특허] Conductive pads defined by embedded traces 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/02
  • H01L-023/64
  • H01L-023/58
출원번호 US-0589359 (2012-08-20)
등록번호 US-8772908 (2014-07-08)
우선권정보 KR-10-2010-0113272 (2010-11-15)
발명자 / 주소
  • Haba, Belgacem
출원인 / 주소
  • Tessera, Inc.
대리인 / 주소
    Lerner, David, Littenberg, Krumholz & Mentlik, LLP
인용정보 피인용 횟수 : 1  인용 특허 : 50

초록

An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surfa

대표청구항

1. An assembly comprising: a first component including a dielectric region having an exposed surface;a continuous groove extending in a path along the surface, the groove having a floor disposed below the surface;a conductive pad exposed at the surface permitting electrical interconnection of the fi

이 특허에 인용된 특허 (50) 인용/피인용 타임라인 분석

  1. Muramatsu Masaharu,JPX ; Akahori Hiroshi,JPX, Back irradiation type light-receiving device and method of making the same.
  2. Malinovich Yacov,ILX ; Koltin Ephie,ILX, Backside illuminated image sensor.
  3. Lin Shi-Tron,TWX ; Chan Chin-Jong,TWX, Bond-pad with a single anchoring structure.
  4. Ming-Tsung Liu (Hsin-Chu TWX) Hsu Bill Y. B. (Chu-Pei TWX) Chung Hsien-Dar (Hu-Wei Town TWX) Wu Der-Yuan (Hsin-Chu TWX), Bonding pad structure and method thereof.
  5. Ding, Yi-Chuan; Lee, Xin Hui; Chen, Kun-Ching, Chip scale package and manufacturing method.
  6. Yamamoto, Koji; Kumamoto, Nobuhisa; Matsumoto, Muneyuki, Damascene interconnection and semiconductor device.
  7. Kida Tsuyoshi,JPX ; Oyachi Kenji,JPX, Electrode structure of semiconductor element.
  8. Hoeberechts Arthur M. E. (Eindhoven NLX) van Gorkom Gerardus G. P. (Eindhoven NLX), Electron-beam device and semiconductor device for use in such an electron-beam device.
  9. Sasaki, Toshiya; Uchiyama, Kazuyoshi; Kawaguchi, Masahiko; Amaya, Keishiro; Tamezawa, Eita, Electronic component having a coil conductor with photosensitive conductive paste.
  10. Holland Christopher E. (Redwood City CA) Westerberg Eugene R. (Palo Alto CA) Madou Marc J. (Palo Alto CA) Otagawa Takaaki (Fremont CA), Etching method for producing an electrochemical cell in a crystalline substrate.
  11. Belgacem Haba, Forming microelectronic connection components by electrophoretic deposition.
  12. Bolom,Tibor; Grunow,Stephan; Rath,David; Simon,Andrew Herbert, Gap free anchored conductor and dielectric structure and method for fabrication thereof.
  13. MacIntyre,Donald M., Hermetic wafer scale integrated circuit structure.
  14. Li,Jiping; Borden,Peter G.; Genio,Edgar B., High throughput measurement of via defects in interconnects.
  15. Harris,Edward Belden; Merchant,Sailesh Mansinh; Steiner,Kurt George; Vitkavage,Susan Clay, Inductor formed in an integrated circuit.
  16. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  17. Noma, Takashi; Shinogi, Hiroyuki; Takao, Yukihiro, Manufacturing method of semiconductor device.
  18. Muthukumar, Sriram; Ramanathan, Shriram, Metal-metal bonding of compliant interconnect.
  19. Lan,Chien Ming, Method for fabricating a probing pad of an integrated circuit chip.
  20. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Method for fabricating chip package.
  21. Tay, Wuu Yean; Tan, Cher Khng Victor, Method for packaging microelectronic devices.
  22. Shiue Ruey-Yun (Hsin-Chu TWX) Wu Wen-Teng (Hsin-Chu TWX) Shieh Pi-Chen (Hsinchu TWX) Liu Chin-Kai (Hsin-Chu TWX), Method of forming bond pad structure for the via plug process.
  23. Lee, Hsin-Hui; Lin, Chia-Fu; Su, Chao-Yuan; Chen, Yen-Ming; Ching, Kai-Ming; Chen, Li-Chih, Method of making a wafer level chip scale package.
  24. Fjelstad, Joseph; Smith, John W., Methods and structures for electronic probing arrays.
  25. Smith John W., Microelectronic connections with liquid conductive elements.
  26. Kirby, Kyle K.; Akram, Salman; Hembree, David R.; Rigg, Sidney B.; Farnworth, Warren M.; Hiatt, William M., Microelectronic devices and methods for forming interconnects in microelectronic devices.
  27. Haba, Belgacem, Microelectronic package element and method of fabricating thereof.
  28. Humpston, Giles; Gao, Guilian; Haba, Belgacem, Microelectronic packages and methods therefor.
  29. Akram Salman, Multi chip semiconductor package and method of construction.
  30. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Haba, Belgacem; Oganesian, Vage, Packaged semiconductor chips.
  31. Badehi Pierre,ILX, Process for manufacturing solder leads on a semiconductor device package.
  32. Sugawa Yoshihisa,JPX ; Tohrin Yasuo,JPX ; Marumoto Yoshinobu,JPX ; Sakakibara Joji,JPX ; Shinotani Ken-ichi,JPX ; Kotera Kohei,JPX ; Ogasawara Kenji,JPX ; Kashihara Keiko,JPX ; Iwami Tomoaki,JPX, Process of impregnating substrate and impregnated substrate.
  33. Yamada, Yuichiro; Hamatani, Tsuyoshi, Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device.
  34. Wood, Alan G.; Doan, Trung Tri, Semiconductor component with backside contacts and method of fabrication.
  35. Yamazaki Toru,JPX, Semiconductor device having inductor element made of first conductive layer of spiral configuration electrically connected to second conductive layer of insular configuration.
  36. Langley Rodney C. (Boise ID), Semiconductor device with improved bond pads.
  37. Katagiri, Mitsuaki; Shirai, Yuji; Nishi, Kunihiko; Ohnishi, Takehiro, Semiconductor integrated circuit device and its manufacturing method.
  38. Thomas Bert Gorczyca ; Udo Heinz Retzlaff DE; Stephan Popp DE, Semiconductor processing article.
  39. Jun Andoh JP; Yoshihiro Morii JP; Toshio Kobayashi JP; Akio Yashiba JP; Hiroshi Takemoto JP; Takeshi Sano JP; Tsutomu Sakatsu JP, Solid-state imaging device and method of production of the same.
  40. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Stackable chip scale semiconductor package with mating contacts on opposed surfaces.
  41. Saran Mukul ; Martin Charles A., System and method for reinforcing a bond pad.
  42. Hsu Chen-Chung (Taichung TWX), Three-dimensional multichip package.
  43. Hedler, Harry; Meyer, Thorsten; Vasquez, Barbara, Transfer wafer level packaging.
  44. Pedder David John,GBX, Trimmable inductor structure.
  45. Wen-Ken Yang TW, Wafer level package and the process of the same.
  46. Chang, Tae-Sub; Lee, Dong-Ho; Son, Min-Young, Wafer level package including ground metal layer.
  47. Geyer,Stefan, Wafer level packages for chips with sawn edge protection.
  48. Kung Ling-Chen,TWX ; Lin Jyh-Rong,TWX ; Chen Kuo-Chuan,TWX, Wafer level packaging method and packages formed.
  49. Lin Mou-Shiung,TWX, Wafer scale packaging scheme.
  50. Umetsu, Kazushige; Kurashima, Yohei; Amako, Jun, Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument.

이 특허를 인용한 특허 (1) 인용/피인용 타임라인 분석

  1. Tiefenböck, Herbert; Burggraf, Jürgen; Pargfrieder, Stefan; Burgstaller, Daniel, Receiving device for receiving semiconductor substrates.

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