Process to make high-K transistor dielectrics
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/00
H01L-021/28
H01L-021/314
출원번호
US-0224059
(2011-09-01)
등록번호
US-8785272
(2014-07-22)
발명자
/ 주소
Yao, Liang-Gi
Wang, Ming-Fang
Chen, Shih-Chang
Liang, Mong-Song
출원인 / 주소
Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
Haynes and Boone, LLP
인용정보
피인용 횟수 :
0인용 특허 :
73
초록▼
A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is ann
A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
대표청구항▼
1. A method of reducing impurities in a high-k dielectric layer, comprising the steps of: providing a substrate;forming a high-k dielectric layer having impurities therein; the high-k dielectric layer being formed by a process that introduces the impurities into the high-k dielectric layer;annealing
1. A method of reducing impurities in a high-k dielectric layer, comprising the steps of: providing a substrate;forming a high-k dielectric layer having impurities therein; the high-k dielectric layer being formed by a process that introduces the impurities into the high-k dielectric layer;annealing the high-k dielectric layer to reduce the impurities within the high-k dielectric layer, wherein annealing the high-k dielectric layer is performed in an ambient selected from the group consisting of H2, H2/N2, O2/N2, He, and Ar to avoid additional oxidation of the high-k dielectric layer; andforming a gate layer upon the annealed high-k dielectric layer. 2. The method of claim 1, wherein the substrate is a silicon substrate;wherein the high-k dielectric layer is a metal oxide or a metal silicate;wherein the process is an MOCVD process; andwherein the impurities in the high-k dielectric layer include carbon impurities. 3. The method of claim 1, wherein the high-k dielectric layer is comprised of a material selected from the group consisting of HfO2, ZrO2, La2O3, Y2O3, Al2O3, TiO2, HfSixOy, ZrSixOy, LaSixOy, YSixOy, AlSixOy, and TiSixOy. 4. The method of claim 1, wherein the high-k dielectric layer is comprised of a material selected from the group consisting of HfO2, ZrO2, Al2O3, HfSixOy and ZrSixOy. 5. The method of claim 1, wherein the high-k dielectric layer anneal is a rapid thermal anneal conducted at a temperature of from about 280 to 820° C. for from about 0.5 to 300 seconds. 6. The method of claim 1, wherein the high-k dielectric layer anneal is a rapid thermal anneal conducted at a temperature of from about 300 to 800° C. for from about 2 to 100 seconds. 7. The method of claim 1, wherein the high-k dielectric layer anneal is a furnace anneal process conducted at a temperature of from about 300 to 800° C. for from about 5 to 300 minutes. 8. The method of claim 1, wherein the high-k dielectric layer anneal is conducted using either rapid thermal processing or a furnace anneal process. 9. The method of claim 1, wherein the high-k dielectric layer anneal is conducted using either a rapid thermal processing or a furnace anneal process using an ambient selected from the group consisting of H2/N2 and O2/N2. 10. The method of claim 1, wherein the high-k dielectric layer anneal is conducted at a temperature of from about 280 to 820° C. using either rapid thermal processing or a furnace anneal process. 11. The method of claim 1, wherein the high-k dielectric layer anneal is conducted at a temperature of from about 300 to 800° C. using either rapid thermal processing or a furnace anneal process with an ambient selected from the group consisting of H2/N2 and O2/N2. 12. The method of claim 1, wherein the high-k dielectric layer has a thickness of from about 5 to 200 Å. 13. The method of claim 1, wherein the high-k dielectric layer has a thickness of from about 20 to 100 Å. 14. The method of claim 1, wherein the gate layer comprised of a material selected from the group consisting of polysilicon, TaN/W, TiN/W, TaN/Al and TiN/Al. 15. The method of claim 1, wherein the gate layer is comprised of polysilicon. 16. The method of claim 1, wherein the gate layer has a thickness of from about 100 to 3000 Å. 17. The method of claim 1, wherein the gate layer has a thickness of from about 500 to 2000 Å. 18. The method of claim 1, wherein the process is an ALCVD process; andwherein the impurities in the high-k dielectric layer include chlorine impurities.
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