IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0398580
(2012-02-16)
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등록번호 |
US-8788882
(2014-07-22)
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발명자
/ 주소 |
- Schroeder, Charles G.
- Graf, Christopher F.
- Nishiguchi, Ciro T.
- D'Souza, Nigel G.
- Baker, Daniel J.
- Magruder, Thomas D.
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출원인 / 주소 |
- National Instruments Corporation
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대리인 / 주소 |
Meyertons Hood Kivlin Kowert & Goetzel, P.C.
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인용정보 |
피인용 횟수 :
6 인용 특허 :
28 |
초록
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Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware elemen
Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.
대표청구항
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1. A method for customizing a test instrument, comprising: providing a plurality of pairs of code modules and an application programming interface (API) for interacting with the plurality of pairs of code modules, wherein each pair of code modules comprises a first code module having program instruc
1. A method for customizing a test instrument, comprising: providing a plurality of pairs of code modules and an application programming interface (API) for interacting with the plurality of pairs of code modules, wherein each pair of code modules comprises a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument;wherein, for each pair of code modules, the first code module and the second code module collectively implement a function in the test instrument, wherein the first code module of a pair of code modules is executable on the processor to perform a first portion of a function, and wherein the second code module of the pair of code modules is configured to be implemented on the programmable hardware element to perform a corresponding second portion of the function;wherein the plurality of pairs of code modules are executable to perform a test operation on a system under test (SUT);receiving user input specifying modification of a second code module of a first one of the plurality of pairs of code modules;wherein other ones of the plurality of pairs of code modules are not affected by the modification of the second code module of the first one of the plurality of pairs of code modules; andgenerating a hardware description for the programmable hardware element of the test instrument based on the modified second code module. 2. The method of claim 1, wherein the user input also specifies modification of the first code module of the at least one of the plurality of pairs of code modules. 3. The method of claim 1, wherein the user input specifies removal of at least a portion of a second code module for a first pair of code modules. 4. The method of claim 1, wherein the user input specifies additional code for the second code module of the at least one of the plurality of pairs of code modules. 5. The method of claim 1, further comprising: configuring the test instrument with the plurality of pairs of code modules, including the at least one of the plurality of pairs of code modules customized based on the user input, wherein said configuring the test instrument comprises: storing the plurality of first code modules in one or more memory mediums of the test instrument for execution by the processor of the test instrument; andconfiguring the programmable hardware element of the test instrument with the hardware description, wherein the hardware description implements the plurality of second code modules. 6. The method of claim 1, wherein the code modules are specified in one or more graphical program portions comprising a plurality of nodes connected by wires, wherein the plurality of nodes visually represent functionality of the one or more graphical program portions;wherein said receiving user input specifying customization comprises receiving user input modifying the one or more graphical program portions. 7. The method of claim 1, wherein the pairs of code modules implement one or more of: hardware configuration, digital signal processing, acquisition, generation, or synchronization. 8. The method of claim 1, wherein the programmable hardware element is configured to interact with underlying hardware of the test instrument. 9. The method of claim 8, wherein the underlying hardware comprises one or more of: analog to digital converters (ADCs);digital to analog converters (DACs);digital input and output;clocking hardware; oranalog gain hardware. 10. The method of claim 1, wherein the API remains unchanged and usable after said receiving user input. 11. The method of claim 1, wherein a portion of each second code module is fixed and is not changeable in response to user input. 12. A non-transitory, computer accessible memory medium storing program instructions for customizing a test instrument, wherein the program instructions are executable to: provide a plurality of pairs of code modules and an application programming interface (API) for interacting with the plurality of pairs of code modules, wherein each pair of code modules comprises a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument, wherein, for each pair of code modules, the first code module and the second code module collectively implement a function in the test instrument, wherein the first code module of a pair of code modules is executable on the processor to perform a first portion of a function, and wherein the second code module of the pair of code modules is configured to be implemented on the programmable hardware element to perform a corresponding second portion of the function;receive user input specifying modification of a second code module of at least one of the plurality of pairs of code modules; andgenerate a hardware description for the programmable hardware element of the test instrument based on the modified second code module. 13. The non-transitory, computer accessible memory medium of claim 11, wherein the user input also specifies modification of the first code module of the at least one of the plurality of pairs of code modules. 14. The non-transitory, computer accessible memory medium of claim 11, wherein the user input specifies removal of at least a portion of a second code module for a first pair of code modules. 15. The non-transitory, computer accessible memory medium of claim 11, wherein the user input specifies additional code for the second code module of the at least one of the plurality of pairs of code modules. 16. The non-transitory, computer accessible memory medium of claim 11, wherein the program instructions are further executable to: configure the test instrument with the plurality of pairs of code modules, including the at least one of the plurality of pairs of code modules customized based on the user input, wherein said configuring the test instrument comprises: storing the plurality of first code modules in one or more memory mediums of the test instrument for execution by the processor of the test instrument; andconfiguring the programmable hardware element of the test instrument with the hardware description, wherein the hardware description implements the plurality of second code modules. 17. The non-transitory, computer accessible memory medium of claim 11, wherein the code modules are specified in one or more graphical program portions comprising a plurality of nodes connected by wires, wherein the plurality of nodes visually represent functionality of the one or more graphical program portions;wherein said receiving user input specifying customization comprises receiving user input modifying the one or more graphical program portions. 18. The non-transitory, computer accessible memory medium of claim 11, wherein the pairs of code modules implement one or more of: hardware configuration, digital signal processing, acquisition, generation, or synchronization. 19. The non-transitory, computer accessible memory medium of claim 11, wherein the programmable hardware element is configured to interact with underlying hardware of the test instrument. 20. The non-transitory, computer accessible memory medium of claim 19, wherein the underlying hardware comprises one or more of: analog to digital converters (ADCs);digital to analog converters (DACs);digital input and output;clocking hardware; oranalog gain hardware. 21. The non-transitory, computer accessible memory medium of claim 11, wherein the API remains unchanged and usable after said receiving user input. 22. The non-transitory, computer accessible memory medium of claim 11, wherein a portion of each second code module is fixed and is not changeable in response to user input. 23. A method for customizing a test instrument, comprising: providing a library of pairs of code modules and an application programming interface (API) for interacting with the plurality of pairs of code modules, wherein each pair of code modules comprises a processor-side code module having program instructions for execution by a processor of the test instrument and a PHE-side code module for implementation on a programmable hardware element (PHE) of the test instrument;wherein, for each pair of code modules, the processor-side code module and the PHE-side code module collectively implement a function in the test instrument, wherein the processor-side code module of a pair of code modules is executable on the processor to perform a first portion of a function, and wherein the PHE-side code module of the pair of code modules is configured to be implemented on the programmable hardware element to perform a corresponding second portion of the function;displaying a first graphical data flow program configured to execute on the processor of the test instrument, wherein the first graphical data flow program comprises a plurality of processor-side code modules; anddisplaying a second graphical data flow program configured to execute on the programmable hardware element of the test instrument, wherein the second graphical data flow program comprises a corresponding plurality of PHE-side code modules corresponding to the plurality of processor-side code modules in the first graphical data flow program;wherein changes to a respective PHE-side code module of a pair does not affect other pairs of code modules in the first and second graphical data flow programs. 24. A method for customizing a test instrument, comprising: providing a library of pairs of code modules and an application programming interface (API) for interacting with the plurality of pairs of code modules, wherein each pair of code modules comprises a processor-side code module having program instructions for execution by a processor of the test instrument and a PHE-side code module for implementation on a programmable hardware element (PHE) of the test instrument;wherein, for each pair of code modules, the processor-side code module and the PHE-side code module collectively implement a function in the test instrument, wherein the processor-side code module of a pair of code modules is executable on the processor to perform a first portion of a function, and wherein the PHE-side code module of the pair of code modules is configured to be implemented on the programmable hardware element to perform a corresponding second portion of the function;displaying a first graphical data flow program configured to execute on the processor of the test instrument, wherein the first graphical data flow program comprises first and second processor-side code modules;displaying a second graphical data flow program configured to execute on the programmable hardware element of the test instrument, wherein the second graphical data flow program comprises corresponding first and second PHE-side code modules corresponding to the first and second processor-side code modules in the first graphical data flow program;wherein the first processor-side code module and the first PHE-side code module correspond to a first pair of code modules, and wherein the second processor-side code module and the second PHE-side code module correspond to a second pair of code modules;receiving user input specifying modification of the first PHE-side code module in the second graphical data flow program;wherein the second PHE-side code module is not affected by the modification of the first PHE-side code module; andgenerating a hardware description for the programmable hardware element of the test instrument based on the modified first PHE-side code module and the second PHE-side code module;wherein the first and second pairs of code modules are executable on the processor and the programmable hardware element, respectively, to perform a test operation on a system under test (SUT).
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