An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor laye
An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
대표청구항▼
1. A semiconductor device comprising: a first line;a second line; anda memory element, the memory element comprising: a capacitor; anda transistor, the transistor comprising: a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalli
1. A semiconductor device comprising: a first line;a second line; anda memory element, the memory element comprising: a capacitor; anda transistor, the transistor comprising: a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region; anda gate electrode with a gate insulating film interposed between the channel formation region and the gate electrode,wherein one of a source and a drain of the transistor is electrically connected to the first line,wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor,wherein the other of the terminals of the capacitor is electrically connected to the second line,wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1014 cm−3, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A. 2. The semiconductor device according to claim 1, wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1019 cm−3. 3. The semiconductor device according to claim 1, wherein the memory element is arranged in matrix. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM. 5. The semiconductor device according to claim 1, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%. 6. A semiconductor device comprising: a first line;a second line; anda memory element, the memory element comprising: a capacitor; anda transistor, the transistor comprising: a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region;a gate electrode; anda first insulating layer over the gate electrode,wherein the channel formation region is provided over the gate electrode with the first insulating layer interposed therebetween,wherein one of a source and a drain of the transistor is electrically connected to the first line,wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor,wherein the other of the terminals of the capacitor is electrically connected to the second line,wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1014 cm−3, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A. 7. The semiconductor device according to claim 6, wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1019 cm−3. 8. The semiconductor device according to claim 6, further comprising a second insulating layer over the channel formation region. 9. The semiconductor device according to claim 6, wherein the memory element is arranged in matrix. 10. The semiconductor device according to claim 6, wherein the semiconductor device is a DRAM. 11. The semiconductor device according to claim 6, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%. 12. A semiconductor device comprising: a memory element, the memory element comprising: a transistor, the transistor comprising: a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region,wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1014 cm−3, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A. 13. The semiconductor device according to claim 12, wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1019 cm−3. 14. The semiconductor device according to claim 12, wherein the memory element is arranged in matrix. 15. The semiconductor device according to claim 12, wherein the semiconductor device is a DRAM. 16. The semiconductor device according to claim 12, wherein the semiconductor device is a SRAM. 17. The semiconductor device according to claim 12, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%. 18. A processor comprising: a timing control circuit;an instruction decoder operationally connected to the timing control circuit;a register array;an address logic and buffer circuit operationally connected to the register array;a data bus interface operationally connected to the register array;an arithmetic logic unit operationally connected to the register array; andan instruction register operationally connected to the instruction decoder and the register array,wherein at least one of the register array and the instruction register comprises a memory element,wherein the memory element comprising a transistor comprising a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region,andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A. 19. The processor according to claim 18, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1014 cm−3. 20. The processor according to claim 18, wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1019 cm−3. 21. The processor according to claim 18, wherein the memory element is arranged in matrix. 22. The processor according to claim 18, wherein the processor is a CPU. 23. The processor according to claim 18, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%. 24. The processor according to claim 18, the transistor comprising: a first gate electrode; anda second gate electrode,wherein the crystalline oxide semiconductor layer is formed over the first gate electrode, andwherein the second gate electrode is formed over the crystalline oxide semiconductor layer. 25. A processor comprising: a register array;an arithmetic logic unit operationally connected to the register array; andan instruction register operationally connected to the arithmetic logic unit,wherein at least one of the register array and the instruction register comprises a memory element,wherein the memory element comprising a transistor comprising a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A. 26. The processor according to claim 25, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1014 cm−3. 27. The processor according to claim 25, wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1019 cm−3. 28. The processor according to claim 25, wherein the memory element is arranged in matrix. 29. The processor according to claim 25, wherein the processor is a CPU. 30. The processor according to claim 25, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%. 31. The processor according to claim 25, the transistor comprising: a first gate electrode; anda second gate electrode,wherein the crystalline oxide semiconductor layer is formed over the first gate electrode, andwherein the second gate electrode is formed over the crystalline oxide semiconductor layer.
Iwasaki, Tatsuya, Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film.
Iwasaki, Tatsuya, Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film.
Iwasaki, Tatsuya, Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film.
Iwasaki, Tatsuya, Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film.
Yano, Koki; Kawashima, Hirokazu; Inoue, Kazuyoshi; Tomai, Shigekazu; Kasami, Masashi, Field effect transistor using oxide semicondutor and method for manufacturing the same.
Hosono,Hideo; Hirano,Masahiro; Ota,Hiromichi; Orita,Masahiro; Hiramatsu,Hidenori; Ueda,Kazushige, LnCuO(S,Se,Te)monocrystalline thin film, its manufacturing method, and optical device or electronic device using the monocrystalline thin film.
Kim Dong-Gyu,KRX ; Lee Won-Hee,KRX, Methods for forming liquid crystal displays including thin film transistors and gate pads having a particular structure.
Levy,David H.; Scuderi,Andrea C.; Irving,Lyn M., Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby.
Hosono,Hideo; Ota,Hiromichi; Orita,Masahiro; Ueda,Kazushige; Hirano,Masahiro; Kamiya,Toshio, Natural-superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film.
Ohde Yuko (Tokyo JPX) Tanaka Hideo (Tokyo JPX) Kuroda Ichiro (Tokyo JPX), Program control system which simultaneously executes a program to be repeated and decrements repetition numbers.
Cillessen Johannes F. M.,NLX ; Blom Paulus W. M.,NLX ; Wolf Ronald M. ; Giesbers Jacobus B.,NLX, Semiconductor device having a transparent switching element.
Morosawa Katsuhiko (Fussa JPX) Wakai Haruo (Mizuhomachi JPX), Semiconductor device having same conductive type MIS transistors, a simple circuit design, and a high productivity.
Ito,Yoshihiro; Kadota,Michio, Semiconductor device in which zinc oxide is used as a semiconductor material and method for manufacturing the semiconductor device.
Shunpei Yamazaki JP; Akiharu Miyanaga JP; Jun Koyama JP; Takeshi Fukunaga JP, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
Ishii,Hiromitsu; Hokari,Hitoshi; Yoshida,Motohiko; Yamaguchi,Ikuhiro, Thin film transistor having an etching protection film and manufacturing method thereof.
Koyama, Jun, Semiconductor device comprising a channel region of a transistor with a crystalline oxide semiconductor and a specific off-state current for the transistor.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.