[특허]Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions

[미국특허] Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-029/739 H01L-031/072
출원번호	US-0483607 (2012-05-30)
등록번호	US-8803198 (2014-08-12)
발명자 / 주소	Smith, Richard Peter Sheppard, Scott T. Saxler, Adam William Wu, Yifeng
출원인 / 주소	Cree, Inc.
대리인 / 주소	Myers Bigel Sibley & Sajovec
인용정보	피인용 횟수 : 1 인용 특허 : 67

초록 ▼

Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about from about 28 to about 70 volts, a gate to source voltage (Vgs) of from about −3.3 to about −14 volts and a normal operat

대표청구항 ▼

1. A Group III Nitride based field effect transistor (FET) having a power degradation of less than about 3.0 dB when operated at from about 9.65 volts/μm to about 24 volts/μm for at least about 10 hours. 2. The FET of claim 1, wherein the FET has a gate to source voltage (Vgs) of from about −3.3 to about −14 volts. 3. The FET of claim 1, wherein the FET is operated at a normal operating temperature for at least about 10 hours. 4. The FET of claim 3, wherein the normal operating temperature is about 140° C. 5. The FET of claim 1, wherein the FET is operated at a temperature of from about 170 to about 180° C. or hotter. 6. The FET of claim 1, comprising a GaN channel layer having a thickness less than about 20 μm. 7. The FET of claim 6, wherein the FET is a high electron mobility transistor (HEMT) and wherein the HEMT further comprises: an AlN layer on the GaN channel layer;an AlGaN layer on the AlN layer;a T-gate contact on the AlGaN layer;an insulating layer on a surface of the HEMT; andsource and drain contacts on the AlGaN layer. 8. The FET of claim 7, further comprising a passivation layer on the T-gate contact, the AlGaN layer and the source and drain contacts, the passivation layer including silicon nitride (SiN). 9. The FET of claim 7 having a power density of greater than about 3.0 W/mm operating at a frequency of from about 3.5 to about 4.0 GHz. 10. The FET of claim 1, wherein the FET is operated at a drain-to-source voltage (VDS) of from about 28 volts to about 70 volts and wherein a drain-to-source distance (LDS) is about 2.9 μm. 11. A Group III Nitride based field effect transistor (FET) capable of withstanding high temperature, reverse bias test conditions of a drain-to-source voltage (VDS) of greater than about 28 volts for at least about 10 hours. 12. The FET of claim 11 having a gate to source voltage (Vgs) of from about −3.3 to about −14 volts. 13. The FET of claim 11, wherein the FET is operated at from about 9.65 volts/μm to about and 24 volts/μm. 14. The FET of claim 13, wherein the FET has a drain-to-source distance (LDS) of about 2.9 μm. 15. The FET of claim 11, wherein the FET is operated at a normal operating temperature for at least about 10 hours. 16. The FET of claim 15, wherein the normal operating temperature is about 140° C. 17. The FET of claim 11 operated at a drain-to-source voltage (VDS) of from about 28 volts to about 70 volts and having a power density of greater than about 3.0 W/mm operating at a frequency of from about 3.5 to about 4.0 GHz. 18. The FET of claim 11, wherein the FET comprises a high electron mobility transistor (HEMT) and wherein the HEMT further comprises: a GaN Channel layer;an AlN layer on the GaN channel layer;an AlGaN layer on the AlN layer;a T-gate contact on the AlGaN layer;an insulating layer on a surface of the HEMT; andsource and drain contacts on the AlGaN layer. 19. The FET of claim 18, wherein the GaN channel layer has a thickness of less than about 20 μm. 20. The FET of claim 18, wherein the insulating layer comprises a passivation layer including silicon nitride (SiN). 21. A Group III Nitride based field effect transistor (FET) having a power degradation of less than about 3.0 dB when operated at less than about 24 volts/μm for at least about 10 hours. 22. The FET of claim 21, wherein the FET has a gate to source voltage (Vgs) of from about −3.3 to about −14 volts. 23. The FET of claim 21, wherein the FET is operated at a drain-to-source voltage (VDS) of from about 28 to about 70 volts and wherein a drain-to-source voltage distance (LDS) is about 2.9 μm.

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[미국특허] Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions 원문보기

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[미국특허] Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions 원문보기

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