초록 ▼

An overvoltage protection devices operable to provide protection against overvoltage events of positive and negative polarity, comprising: an N P N semiconductor structure defining: a first N-type region; a first P-type region; and a second N-type region; wherein one of the first or second N-type re

An overvoltage protection devices operable to provide protection against overvoltage events of positive and negative polarity, comprising: an N P N semiconductor structure defining: a first N-type region; a first P-type region; and a second N-type region; wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference, and wherein a field plate is in electrical contact with the first P-type region, and the field plate overlaps with but is isolated from portions of the first and second N type regions.

대표청구항 ▼

1. An overvoltage protection device configured to provide protection against overvoltage events of positive and negative polarity, comprising: an NPN transistor having a collector, a base, and an emitter, the NPN transistor comprising: a first N-type region configured as the collector or the emitter

1. An overvoltage protection device configured to provide protection against overvoltage events of positive and negative polarity, comprising: an NPN transistor having a collector, a base, and an emitter, the NPN transistor comprising: a first N-type region configured as the collector or the emitter;a first P-type region configured as the base; anda second N-type region configured as the collector or the emitter;wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference voltage; anda relatively highly doped P-type region having a higher doping concentration than the first P-type region;wherein a field plate is in electrical contact with the first P-type region, the field plate extending from over at least a portion of the first N-type region to over at least a portion of the second N-type region, and the field plate being isolated from the portion of the first N-type region and the portion of the second N-type region;wherein the first P-type region is disposed between the relatively highly doped P-type region and the field plate, and wherein the relatively highly doped P-type region is configured to protect the overvoltage protection device from an external potential causing a depletion region that interferes with operation of the overvoltage protection device. 2. The overvoltage protection device as claimed in claim 1, further including a second P-type region within at least one of the first or second N-type regions, thereby forming a PNP structure with the relevant one of the first or second N-type regions and the first P-type region. 3. The overvoltage protection device as claimed in claim 2, in which the NPN transistor and the PNP structure cooperate to form a silicon controlled rectifier arrangement. 4. The overvoltage device as claimed in claim 1, in which the first and second N-type regions have substantially the same dopant concentration as each other. 5. The overvoltage device as claimed in claim 1, in which the first N-type region has a second P-type region formed therein, and wherein a first distance exists between a boundary between the first N-type region and the first P-type region, and the second P-type region. 6. The overvoltage device as claimed in claim 5, in which the second N-type region has a third P-type region formed therein and where a second distance exists between a boundary between the second N-type region and the first P-type region and the third P-type region. 7. The overvoltage protection device as claimed in claim 5, in which the first distance between the second P-type region and the boundary between the first N-type region and the first P-type region is defined during masking steps during the manufacture of the protection device. 8. The overvoltage protection device as claimed in claim 5, in which the first distance controls a threshold voltage of the protection device. 9. The overvoltage protection device as claimed in claim 6, in which the second distance between the third P-type region and the boundary between the second N-type region and the first P-type region is defined during masking steps during the manufacture of the protection device. 10. The overvoltage protection device as claimed in claim 6, in which the second distance controls a threshold voltage of the protection device. 11. The overvoltage protection device as claimed in claim 1, in which the first P-type region is configured to float during operation. 12. The overvoltage protection device as claimed in claim 1, further comprising a trigger circuit connected to the first P-type region configured to switch the protection device on after a threshold voltage has been reached. 13. The overvoltage protection device as claimed in claim 12, in which the trigger circuit is configured to conduct after a voltage difference across it exceeds a predetermined magnitude. 14. The overvoltage protection device as claimed in claim 1 further comprising a first impedance connected to the first P-type region for controlling current flow therein once the protection device has become conducting. 15. The overvoltage protection device as claimed in claim 14, in which the first impedance is configured to control a foldback voltage of the protection device. 16. The overvoltage protection device as claimed in claim 14 in which the first impedance comprises a resistor. 17. The overvoltage protection device as claimed in claim 14, in which the first impedance comprises an inductor. 18. The overvoltage protection device as claimed in claim 14, in which the first impedance comprises a capacitor. 19. The overvoltage protection device as claimed in claim 14, in which the first impedance comprises at least one transistor responsive to a control circuit. 20. The overvoltage protection device as claimed in claim 14, further comprising a second impedance connected to at least one of the first or second N-type regions for controlling current flow in the protection device. 21. The overvoltage protection device as claimed in claim 20, in which the relative impedance of the first and second impedances are configured to control a foldback voltage of the protection device. 22. The overvoltage protection device as claimed in claim 1, in which the NPN transistor of the protection device is disposed in an insulated well having sidewalls and a layer of insulation over a substrate, and wherein the relatively highly doped P-type region is disposed adjacent the layer of insulation within the insulated well. 23. The overvoltage protection device as claimed in claim 1, wherein the overvoltage protection device is embodied in an integrated circuit. 24. An overvoltage protection device configured to provide protection against overvoltage events of positive and negative polarity, comprising: a PNP transistor having a collector, a base, and an emitter, the PNP transistor comprising: a first P-type region configured as the collector or the emitter;a first N-type region configured as the base; anda second P-type region configured as the collector or the emitter;wherein one of the first or second P-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second P-type regions is connected to a reference voltage;a relatively highly doped N-type region having a higher doping concentration than the first N-type region; andwherein a field plate is in electrical contact with the first N-type region, the field plate extending from over at least a portion of the first P-type region to over at least a portion of the second P-type region, and the field plate being isolated from the portion of the first P-type region and the portion of the second P-type region;wherein the first N-type region is disposed between the relatively highly doped N-type region and the field plate, and wherein the relatively highly doped N-type region is configured to protect the overvoltage protection device from an external potential causing a depletion region that interferes with operation of the overvoltage protection device. 25. The overvoltage protection device as claimed in claim 24, further comprising a lateral bipolar transistor wherein collector and emitter regions have substantially the same doping concentrations, and wherein at least one of the collector or emitter further contains a region of material of the same type as the base region spaced apart from the base region and wherein the spacing and dopant concentration control punch through driven conduction in the protection device. 26. The overvoltage protection device as claimed in claim 24, wherein the PNP transistor is disposed within an insulated well having sidewalls and a layer of insulation over a substrate, and wherein the relatively highly doped N-type region is disposed adjacent the layer of insulation. 27. The overvoltage protection device as claimed in claim 26, further comprising a guard ring of N-type material having a higher doping concentration than the first N-type region, wherein the guard ring is disposed adjacent to the sidewalls within the insulated well and the PNP transistor. 28. The overvoltage protection device as claimed in claim 22, further comprising a guard ring of P-type material having a higher doping concentration than the first P-type region, wherein the guard ring is disposed adjacent to the sidewalls within the insulated well. 29. An overvoltage protection device configured to provide protection against overvoltage events of positive and negative polarity, comprising: an NPN transistor disposed within an insulated well having sidewalls and a layer of insulation over a substrate, the NPN transistor having a collector, a base, and an emitter, the NPN transistor comprising: a first N-type region configured as the collector or the emitter;a first P-type region configured as the base; anda second N-type region configured as the collector or the emitter;wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference voltage; anda relatively highly doped P-type region having a higher doping concentration than the first P-type region, the relatively highly doped P-type region disposed in the insulated well and adjacent the layer of insulation; anda guard ring of P-type material having a higher doping concentration than the first P-type region, wherein the guard ring is disposed adjacent to the sidewalls within the insulated well and the NPN transistor;wherein a field plate is in electrical contact with the first P-type region, the first P-type region being disposed between the field plate and the relatively highly doped P-type region, the field plate extending from over at least a portion of the first N-type region to over at least a portion of the second N-type region, and the field plate being isolated from the portion of the first N-type region and the portion of the second N-type region. 30. The overvoltage protection device as claimed in claim 29, wherein a portion of the first P-type region is disposed between the relatively highly doped P-type region and the guard ring. 31. The overvoltage protection device as claimed in claim 1, wherein the first P-type region extends over the entire relatively highly doped P-type region. 32. The overvoltage protection device as claimed in claim 1, wherein the field plate is in direct contact with a P-type interface region having enhanced P-type doping relative to the first P-type region, and wherein the field plate is in electrical contact with the first P-type region at least partly via the P-type interface region. 33. The overvoltage protection device as claimed in claim 24 wherein the first N-type region extends over the entire relatively highly doped N-type region.