최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0422057 (2012-03-16) |
등록번호 | US-8823122 (2014-09-02) |
발명자 / 주소 |
|
출원인 / 주소 |
|
인용정보 | 피인용 횟수 : 0 인용 특허 : 339 |
An integrated device, the device including a first crystalline layer covered by an oxide layer, a second crystalline layer overlying the oxide layer, wherein the first and second crystalline layers are image sensor layers, and the device includes a third crystalline layer, wherein the third crystall
An integrated device, the device including a first crystalline layer covered by an oxide layer, a second crystalline layer overlying the oxide layer, wherein the first and second crystalline layers are image sensor layers, and the device includes a third crystalline layer, wherein the third crystalline layer includes single crystal transistors.
1. An integrated device, comprising: a first crystalline layer covered by an oxide layer,a second crystalline layer overlying said oxide layer, wherein said first and second crystalline layers are image sensor layers,and said device comprises a third crystalline layer, wherein said third crystalline
1. An integrated device, comprising: a first crystalline layer covered by an oxide layer,a second crystalline layer overlying said oxide layer, wherein said first and second crystalline layers are image sensor layers,and said device comprises a third crystalline layer, wherein said third crystalline layer comprises single crystal transistors. 2. An integrated device according to claim 1, wherein at least one of said image sensor layers and said single crystal transistors are aligned to each other. 3. An integrated device according to claim 1, wherein said first crystalline layer is sensitive to a different spectrum than said second crystalline layer. 4. An integrated device according to claim 1, wherein said first crystalline layer has at least an order of magnitude difference in light sensitivity than said second crystalline layer. 5. An integrated device according to claim 1, wherein at least one of said image sensor layers comprises a polarizer. 6. An integrated device according to claim 1, wherein said single crystal transistors form a plurality of pixel control circuits. 7. An integrated image sensor, comprising: a first mono-crystal layer to comprise a plurality of image sensor pixels and alignment marks, andan oxide layer overlaying and on top of said first mono-crystal layer, anda second mono-crystal layer to comprise a plurality of second image sensor pixels aligned to said alignment marks, and said second mono-crystal layer overlaying said oxide layer, anda third mono-crystal layer, wherein said third mono-crystal layer to comprise a plurality of single crystal transistors aligned to said alignment marks. 8. An integrated device according to claim 7, wherein said third mono-crystal layer is less than 2 microns thick. 9. An integrated device according to claim 7, wherein said aligned comprises less than 1 micron alignment error. 10. An integrated device according to claim 7, wherein said first mono-crystal layer is sensitive to a different spectrum than said second mono-crystal layer. 11. An integrated device according to claim 7, wherein said first mono-crystal layer has at least an order of magnitude difference in light sensitivity than said second mono-crystal layer. 12. An integrated device according to claim 7, wherein at least one of said first mono-crystal and said second mono-crystal layers is less than 2 microns thick. 13. An integrated device according to claim 7, wherein at least one of said first mono-crystal and said second mono-crystal layers comprise a polarizer. 14. An integrated device according to claim 7, wherein said single crystal transistors form a plurality of pixel control circuits. 15. An integrated device, comprising: a first mono-crystal layer to comprise a plurality of single crystal transistors and alignment marks, andan overlaying oxide on top of said first mono-crystal layer, anda second mono-crystal layer overlaying said oxide, and wherein said second mono-crystal layer to comprise a plurality of image sensor pixels aligned to said alignment marks. 16. An integrated device according to claim 15, wherein said second mono-crystal layer is less than 2 microns thick. 17. An integrated device according to claim 15, wherein said image sensor pixels and said single crystal transistors are aligned to each other. 18. An integrated device according to claim 15, wherein said second mono-crystal layer comprises two crystalline layers, wherein;said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;said first image sensor layer is sensitive to a different spectrum than said second image sensor layer. 19. An integrated device according to claim 15, wherein said second mono-crystal layer comprises two crystalline layers, wherein;said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;said first image sensor layer has at least an order of magnitude difference in light sensitivity than said second image sensor layer. 20. An integrated device according to claim 15, wherein said second mono-crystal layer comprises two crystalline layers, wherein;said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;at least one of said two crystalline layers is less than 2 microns thick. 21. An integrated device according to claim 15, wherein said second mono-crystal layer comprises a polarizer. 22. An integrated device according to claim 15, wherein said single crystal transistors form a plurality of pixel control circuits.
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