초록 ▼

A fault diagnostic circuit (100) and associated method of operation are described for testing an FET device (114) for a gate-drain short failure (113) by floating the FET gate during a predetermined test period and then comparing (118) the FET output voltage (115) at the source to a predetermined th

A fault diagnostic circuit (100) and associated method of operation are described for testing an FET device (114) for a gate-drain short failure (113) by floating the FET gate during a predetermined test period and then comparing (118) the FET output voltage (115) at the source to a predetermined threshold voltage (VTHRESHOLD) which may be selected as a percentage of the power supply voltage (VPOWER) for the FET device to determine if the FET output voltage is greater than the threshold voltage, in which case a device fault is signaled (119).

대표청구항 ▼

1. A switching device with built-in fault detection comprising: a power switch for connecting a power supply voltage that is coupled to a drain terminal to an output load arrangement that is coupled to a source terminal under control of a gate terminal;a cutoff circuit coupled between the gate termi

1. A switching device with built-in fault detection comprising: a power switch for connecting a power supply voltage that is coupled to a drain terminal to an output load arrangement that is coupled to a source terminal under control of a gate terminal;a cutoff circuit coupled between the gate terminal of the power switch and a gate signal source for floating the gate terminal during a predetermined diagnostic event; anda failure detection circuit for detecting a gate-drain short in the power switch by comparing a signal voltage at the source terminal of the power switch with a threshold voltage during the predetermined diagnostic event and providing an output fault signal only when the signal voltage is greater than the threshold voltage. 2. The switching device of claim 1, where the power switch, cutoff circuit, and failure detection circuit are formed in a single integrated Power Quad Flat Pack No Lead (PQFN) package. 3. The switching device of claim 1, where the power switch comprises an n-channel NMOSFET switch with on-resistance ranging from 10 milliohms to 35 milliohms. 4. The switching device of claim 1, where the cutoff circuit comprises a transmission gate coupled between the gate terminal of the power switch and a microprocessor that generates the gate signal source. 5. The switching device of claim 1, where the failure detection circuit comprises a comparator circuit which compares the signal voltage to the threshold voltage when the gate terminal of the power switch is floating and provides the output fault signal as an output of the comparator circuit only when the signal voltage greater than the threshold voltage. 6. The switching device of claim 1, where the failure detection circuit provides the output fault signal by setting a serial protocol interface bus fault register flag or hardware fault flag. 7. The switching device of claim 1, where the threshold voltage represents a predetermined percentage of the power supply voltage. 8. The switching device of claim 1, further comprising a fault containment circuit for preventing the gate terminal at the power switch from floating after the failure detection circuit detects that the signal voltage is greater than the threshold voltage during a predetermined diagnostic event. 9. The switching device of claim 1, further comprising an anti-fuse for coupling a reset input to the power supply voltage after the failure detection circuit detects that the signal voltage is greater than the threshold voltage during a predetermined diagnostic event, thereby preventing the switching device from entering a sleep mode. 10. The switching device of claim 1, where the output fault signal is used to notify a user that the power switch is defective. 11. The switching device of claim 1, where the power switch, cutoff circuit and failure detection circuit are controlled by signals from an external microcontroller unit to detecting the gate-drain short in the power switch during the predetermined diagnostic event. 12. The switching device of claim 1, further comprising a processor circuit for receiving the output fault signal from the failure detection circuit and for generating an event signal to trigger a fault containment event in response to the output fault signal. 13. A method for testing an integrated circuit field effect transistor (FET) device that is drain-source coupled between power supply and an output load under control of a gate electrode, the method comprising: floating the gate electrode of the FET device;comparing a source voltage at the source of the FET device to a predetermined threshold voltage to detect a gate-drain short in the FET device if the source voltage exceeds the predetermined threshold voltage; andlogging a fault if a gate-drain short in the FET device is detected. 14. The method of claim 13, where the method for testing occurs during a sleep mode. 15. The method of claim 13, where floating the gate electrode comprises activating a cutoff circuit coupled between the gate electrode of the FET device and a gate signal source for floating the gate electrode during a predetermined diagnostic event. 16. The method of claim 13, where logging the fault comprises setting a serial protocol interface bus fault register flag or hardware fault flag. 17. The method of claim 13, further comprising preventing the gate electrode at the FET device from floating in response to detecting a gate-drain short at the FET device. 18. The method of claim 13, further comprising preventing the FET device from entering a sleep mode by connecting a reset input to a power supply upon detection of the fault. 19. The method of claim 13, further comprising notifying an automotive system user that the FET device is defective and needs to be serviced in response to detecting a gate-drain short at the FET device. 20. A failure diagnostics system comprising: a drive switch operable to provide a drive signal at an output in response to a gate signal supplied to a gate of the drive switch; anda diagnostic circuit arrangement for floating the gate of the drive switch during a predetermined diagnostic event and detecting a gate-drain short of the drive switch by comparing the output from the drive switch with a threshold voltage representing a predetermined percentage of a power supply voltage for the drive switch, thereby providing an output fault signal only when the output from the drive switch is greater than the threshold voltage.