초록 ▼

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the fir

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

대표청구항 ▼

1. A semiconductor chip comprising: a semiconductor substrate;a MOS device in or on said semiconductor substrate;a first patterned circuit layer over said semiconductor substrate, wherein said first patterned circuit layer comprises a copper portion and a first conductive layer at a bottom and a sid

1. A semiconductor chip comprising: a semiconductor substrate;a MOS device in or on said semiconductor substrate;a first patterned circuit layer over said semiconductor substrate, wherein said first patterned circuit layer comprises a copper portion and a first conductive layer at a bottom and a sidewall of said copper portion;a first dielectric layer over said first patterned circuit layer and said semiconductor substrate, wherein a first opening in said first dielectric layer is over a first contact point of a first conductive interconnect of said first patterned circuit layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said first dielectric layer is over a second contact point of a second conductive interconnect of said first patterned circuit layer, and said second contact point is at a bottom of said second opening, wherein said first conductive interconnect has a portion spaced apart from said second conductive interconnect;a second patterned circuit layer over said first dielectric layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second patterned circuit layer, wherein said second patterned circuit layer comprises an aluminum-containing layer;a second dielectric layer on said second patterned circuit layer and over said first dielectric layer, wherein a third opening in said second dielectric layer is over a third contact point of said second patterned circuit layer, and said third contact point is at a bottom of said third opening, wherein said third contact point is connected to said first contact point through said first opening, and said third contact point is connected to said second contact point through said second opening; anda conductive bump on said third contact point and a first surface of said second dielectric layer and vertically over said first and second contact points. 2. The semiconductor chip of claim 1, wherein said conductive bump comprises a titanium-containing layer on said third contact point and said first surface of said second dielectric layer and a gold layer having a thickness between 2and 30 micrometers coupled to said titanium-containing layer. 3. The semiconductor chip of claim 1 further comprising a polymer layer on said first dielectric layer, wherein a fourth opening in said polymer layer is coupled to said first contact point, and a fifth opening in said polymer layer is coupled to said second contact point, wherein said second patterned circuit layer is further on said polymer layer. 4. The semiconductor chip of claim 1, wherein said conductive bump comprises a second conductive layer on said third contact point and said first surface of said second dielectric layer and a copper layer having a thickness between 2 and 30 micrometers coupled to said second conductive layer. 5. The semiconductor chip of claim 1 further comprising a polymer layer on said first dielectric layer, wherein said polymer layer has a thickness between 5and 20 micrometers, wherein a fourth opening in said polymer layer is coupled to said first contact point, and a fifth opening in said polymer layer is coupled to said second contact point, wherein said second patterned circuit layer is further on said polymer layer. 6. The semiconductor chip of claim 1, wherein said conductive bump comprises a second conductive layer on said third contact point and said first surface of said second dielectric layer and a copper layer having a thickness between 1 and 200 micrometers coupled to said second conductive layer. 7. The semiconductor chip of claim 1, wherein said conductive bump comprises a second conductive layer on said third contact point and said first surface of said second dielectric layer and a nickel-containing layer coupled to said second conductive layer. 8. The semiconductor chip of claim 1, wherein said first conductive layer comprises tantalum. 9. The semiconductor chip of claim 1, wherein said first dielectric layer comprises a nitride. 10. The semiconductor chip of claim 1, wherein said first dielectric layer comprises an oxide. 11. The semiconductor chip of claim 1, wherein said second dielectric layer comprises a polymer. 12. The semiconductor chip of claim 1, wherein said first opening has a maximum transverse dimension between 0.05 and 25 micrometers. 13. The semiconductor chip of claim 1, wherein said first opening has a length between 0.05 and 25 micrometers. 14. The semiconductor chip of claim 1, wherein said aluminum-containing layer has a thickness between 0.01 and 3 micrometers. 15. A semiconductor chip comprising: a semiconductor substrate;a MOS device in or on said semiconductor substrate;a first patterned circuit layer over said semiconductor substrate, wherein said first patterned circuit layer comprises a copper portion and a first conductive layer at a bottom and a sidewall of said copper portion;a first dielectric layer over said first patterned circuit layer and said semiconductor substrate, wherein a first opening in said first dielectric layer is over a first contact point of a first conductive interconnect of said first patterned circuit layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said first dielectric layer is over second contact point of a second conductive interconnect of said first patterned circuit layer, and said second contact point is at a bottom of said second opening, wherein said first conductive interconnect has a portion spaced apart from said second conductive interconnect;a second patterned circuit layer over said first dielectric layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second patterned circuit layer, wherein said second patterned circuit layer comprises a second conductive layer and a third conductive layer on said second conductive layer, wherein said second conductive layer is at a bottom of said third conductive layer but not at a sidewall of said third conductive layer;a second dielectric layer on said second patterned circuit layer and over said first dielectric layer, wherein a third opening in said second dielectric layer is over a third contact point of said second patterned circuit layer, and said third contact point is at a bottom of said third opening, wherein said third contact point is connected to said first contact point through said first opening, and said third contact point is connected to said second contact point through said second opening; anda conductive bump on said third contact point and a first surface of said second dielectric layer and vertically over said first and second contact points. 16. The semiconductor chip of claim 15, wherein said conductive bump comprises a titanium-containing layer on said third contact point and said first surface of said second dielectric layer and a gold layer having a thickness between 2and 30 micrometers coupled to said titanium-containing layer. 17. The semiconductor chip of claim 15 further comprising a polymer layer on said first dielectric layer, wherein a fourth opening in said polymer layer is coupled to said first contact point, and a fifth opening in said polymer layer is coupled to said second contact point, wherein said second patterned circuit layer is further on said polymer layer. 18. The semiconductor chip of claim 15, wherein said conductive bump comprises a fourth conductive layer on said third contact point and said first surface of said second dielectric layer and a copper layer having a thickness between 2 and 30 micrometers coupled to said fourth conductive layer. 19. The semiconductor chip of claim 15 further comprising a polymer layer on said first dielectric layer, wherein said polymer layer has a thickness between 5 and 20 micrometers, wherein a fourth opening in said polymer layer is coupled to said first contact point, and a fifth opening in said polymer layer is coupled to said second contact point, wherein said second patterned circuit layer is further on said polymer layer. 20. The semiconductor chip of claim 15, wherein said conductive bump comprises a fourth conductive layer on said third contact point and said first surface of said second dielectric layer and a copper layer having a thickness between 1 and 200 micrometers coupled to said fourth conductive layer. 21. The semiconductor chip of claim 15, wherein said conductive bump comprises a fourth conductive layer on said third contact point and said first surface of said second dielectric layer and a nickel-containing layer coupled to said fourth conductive layer. 22. The semiconductor chip of claim 15, wherein said first conductive layer comprises tantalum. 23. The semiconductor chip of claim 15, wherein said first dielectric layer comprises an oxide. 24. The semiconductor chip of claim 15, wherein said first dielectric layer comprises a nitride. 25. The semiconductor chip of claim 15, wherein said second dielectric layer comprises a polymer. 26. The semiconductor chip of claim 15, wherein said first opening has a maximum transverse dimension between 0.05 and 25 micrometers. 27. The semiconductor chip of claim 15, wherein said first opening has a length between 0.05 and 25 micrometers. 28. The semiconductor chip of claim 15, wherein said second conductive layer comprises titanium. 29. The semiconductor chip of claim 15, wherein said third conductive layer comprises a copper layer having a thickness between 1 and 35 micrometers. 30. A semiconductor chip comprising: a semiconductor substrate;a MOS device in or on said silicon substrate;a first patterned circuit layer over said semiconductor substrate, wherein said first patterned circuit layer comprises a copper portion and a conductive layer at a bottom and a sidewall of said copper portion;a separating layer over said first patterned circuit layer and said semiconductor substrate, wherein a first opening in said separating layer is over a first contact point of a first conductive interconnect of said first patterned circuit layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of a second conductive interconnect of said first patterned circuit layer, and said second contact point is at a bottom of said second opening, wherein said first conductive interconnect has a portion spaced apart from said second conductive interconnect;a second patterned circuit layer over said separating layer and said first patterned circuit layer, said second patterned circuit layer having a first surface on said first and second contact points and a second surface opposite said first surface, wherein said first contact point is connected to said second contact point through said second patterned circuit layer, wherein said second patterned circuit layer comprises an aluminum-containing layer;a first polymer layer directly on a first portion of said second surface of said second patterned circuit layer, wherein an opening in said first polymer layer exposes a second portion of said second surface of said second patterned circuit layer; anda conductive bump over a top surface of said second patterned circuit layer and vertically over said first and second contact points. 31. The semiconductor chip of claim 30 further comprising a second polymer layer on said separating layer, wherein a third opening in said second polymer layer is coupled to said first and second contact points, wherein said second patterned circuit layer is further coupled to said second polymer layer. 32. The semiconductor chip of claim 30 further comprising a second polymer layer on said separating layer, wherein said second polymer layer has a thickness between 5 and 20 micrometers, wherein a third opening in said second polymer layer is coupled to said first and second contact points, wherein said second patterned circuit layer is further coupled to said second polymer layer. 33. The semiconductor chip of claim 30, wherein said conductive layer comprises tantalum. 34. The semiconductor chip of claim 30, wherein said separating layer comprises a nitride. 35. The semiconductor chip of claim 30, wherein said separating layer comprises an oxide. 36. The semiconductor chip of claim 30, wherein said first opening has a maximum transverse dimension between 0.05 and 25 micrometers. 37. The semiconductor chip of claim 30, wherein said first opening has a length between 0.05 and 25 micrometers. 38. The semiconductor chip of claim 30, wherein said aluminum-containing layer has a thickness between 0.01 and 3 micrometers. 39. A semiconductor chip comprising: a semiconductor substrate;a MOS device in or on said semiconductor substrate;a first patterned circuit layer over said semiconductor substrate, wherein said first patterned circuit layer comprises a copper portion and a first conductive layer at a bottom and a sidewall of said copper portion;a separating layer over said first patterned circuit layer and said semiconductor substrate, wherein a first opening in said separating layer is over a first contact point of a first conductive interconnect of said first patterned circuit layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of a second conductive interconnect of said first patterned circuit layer, and said second contact point is at a bottom of said second opening, wherein said first conductive interconnect has a portion spaced apart from said second conductive interconnect;a second patterned circuit layer over said separating layer and said first patterned circuit layer, said second patterned circuit layer having a first surface on said first and second contact points and a second surface opposite said first surface, wherein said first contact point is connected to said second contact point through said second patterned circuit layer, wherein said second patterned circuit layer comprises a second conductive layer and a third conductive layer on said second conductive layer, wherein said second conductive layer is at a bottom of said third conductive layer but not at a sidewall of said third conductive layer;a first polymer layer directly on a first portion of said second surface of said second patterned circuit layer, wherein an opening in said first polymer layer exposes a second portion of said second surface of said second patterned circuit layer; anda conductive bump over a top surface of said second patterned circuit layer and vertically over said first and second contact points. 40. The semiconductor chip of claim 39 further comprising a second polymer layer on said separating layer, wherein a third opening in said second polymer layer is coupled to said first and second contact points, wherein said second patterned circuit layer is further coupled to said second polymer layer. 41. The semiconductor chip of claim 39 further comprising a second polymer layer on said separating layer, wherein said second polymer layer has a thickness between 5 and 20 micrometers, wherein a third opening in said second polymer layer is coupled to said first and second contact points, wherein said second patterned circuit layer is further coupled to said second polymer layer. 42. The semiconductor chip of claim 39, wherein said first conductive layer comprises tantalum. 43. The semiconductor chip of claim 39, wherein said separating layer comprises a nitride. 44. The semiconductor chip of claim 39, wherein said separating layer comprises an oxide. 45. The semiconductor chip of claim 39, wherein said first opening has a maximum transverse dimension between 0.05 and 25 micrometers. 46. The semiconductor chip of claim 39, wherein said first opening has a length between 0.05 and 25 micrometers. 47. The semiconductor chip of claim 39, wherein said second conductive layer comprises titanium. 48. The semiconductor chip of claim 39, wherein said third conductive layer comprises a copper layer having a thickness between 1 and 35 micrometers.